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Searched refs:vext_ver (Results 1 – 4 of 4) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dmachine.c370 VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
H A Dcpu.h220 target_ulong vext_ver; member
H A Dcpu.c1356 cpu->env.vext_ver = VEXT_VERSION_1_00_0; in riscv_cpu_init()
1876 cpu->env.vext_ver = VEXT_VERSION_1_00_0; in prop_vext_spec_set()
/openbmc/qemu/target/riscv/tcg/
H A Dtcg-cpu.c1354 env->vext_ver = VEXT_VERSION_1_00_0; in riscv_init_max_cpu_extensions()