Searched refs:tmdsck (Results 1 – 1 of 1) sorted by relevance
79 u32 val, tmdsck, idf, odf, pllctrl = 0; in sti_hdmi_tx3g4c28phy_start() local102 tmdsck = ckpxpll; in sti_hdmi_tx3g4c28phy_start()105 if (tmdsck > 340000000) { in sti_hdmi_tx3g4c28phy_start()106 DRM_ERROR("output TMDS clock (%d) out of range\n", tmdsck); in sti_hdmi_tx3g4c28phy_start()138 if (tmdsck > 165000000) in sti_hdmi_tx3g4c28phy_start()147 if ((hdmiphy_config[i].min_tmds_freq <= tmdsck) && in sti_hdmi_tx3g4c28phy_start()148 (hdmiphy_config[i].max_tmds_freq >= tmdsck)) { in sti_hdmi_tx3g4c28phy_start()