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Searched refs:tcg_debug_assert (Results 1 – 25 of 58) sorted by relevance

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/openbmc/qemu/accel/tcg/
H A Dldst_common.c.inc18 tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_8);
25 tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_16);
32 tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_32);
39 tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_64);
69 tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_128);
85 tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_8);
92 tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_16);
99 tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_32);
106 tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_64);
113 tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_128);
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H A Dtranslator.c147 tcg_debug_assert(db->is_jmp == DISAS_NEXT); /* no early exit */ in translator_loop()
152 tcg_debug_assert(db->is_jmp == DISAS_NEXT); /* no early exit */ in translator_loop()
164 tcg_debug_assert(db->is_jmp == DISAS_NEXT); /* no early exit */ in translator_loop()
213 tcg_debug_assert(first_insn_start == db->insn_start); in translator_loop()
215 tcg_debug_assert(first_insn_start != db->insn_start); in translator_loop()
259 tcg_debug_assert(db->max_insns == 1); in translator_ld()
H A Dinternal-common.h118 #define assert_memory_lock() tcg_debug_assert(have_mmap_lock())
/openbmc/qemu/tcg/
H A Dtcg-op-ldst.c44 tcg_debug_assert(a_bits + 5 <= TARGET_PAGE_BITS); in check_max_alignment()
300 tcg_debug_assert(addr_type == tcg_ctx->addr_type); in tcg_gen_qemu_st_i32_int()
301 tcg_debug_assert((memop & MO_SIZE) <= MO_32); in tcg_gen_qemu_st_i32_int()
346 tcg_debug_assert(addr_type == tcg_ctx->addr_type); in tcg_gen_qemu_ld_i64_int()
347 tcg_debug_assert((memop & MO_SIZE) <= MO_32); in tcg_gen_qemu_ld_i64_int()
412 tcg_debug_assert(addr_type == tcg_ctx->addr_type); in tcg_gen_qemu_st_i64_int()
413 tcg_debug_assert((memop & MO_SIZE) <= MO_64); in tcg_gen_qemu_st_i64_int()
466 tcg_debug_assert(addr_type == tcg_ctx->addr_type);
467 tcg_debug_assert((memop & MO_SIZE) <= MO_64); in canonicalize_memop_i128_as_i64()
669 tcg_debug_assert(addr_typ in tcg_gen_qemu_st_i128_int()
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H A Dtcg-op-vec.c197 tcg_debug_assert(at->base_type >= type); in vec_gen_op2()
210 tcg_debug_assert(at->base_type >= type); in vec_gen_op3()
211 tcg_debug_assert(bt->base_type >= type); in vec_gen_op3()
295 tcg_debug_assert(low_type >= TCG_TYPE_V64); in tcg_gen_stl_vec()
296 tcg_debug_assert(low_type <= type); in tcg_gen_stl_vec()
378 tcg_debug_assert(at->base_type >= type); in do_op2()
426 tcg_debug_assert(tcg_can_emit_vec_op(INDEX_op_sub_vec, type, vece)); in tcg_gen_abs_vec()
456 tcg_debug_assert(at->base_type == type); in do_shifti()
457 tcg_debug_assert(i >= 0 && i < (8 << vece)); in do_shifti()
473 tcg_debug_assert(can < 0); in do_shifti()
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H A Dtcg.c361 tcg_debug_assert(!l->has_value); in tcg_out_label()
507 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); in tcg_out_movext()
562 tcg_debug_assert(scratch >= 0); in tcg_out_movext2()
621 tcg_debug_assert(scratch >= 0); in tcg_out_movext3()
636 tcg_debug_assert(scratch >= 0); in tcg_out_movext3()
1300 tcg_debug_assert(b >= 0 && b < n); in tcg_register_thread()
1538 tcg_debug_assert(stk_slot < max); in arg_slot_stk_ofs()
1854 tcg_debug_assert(!tcg_regset_test_reg(s->reserved_regs, TCG_AREG0)); in tcg_context_init()
1911 tcg_debug_assert(result == 0); in tcg_prologue_init()
1960 tcg_debug_assert(tcg_code_gen_epilogu in tcg_prologue_init()
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H A Dtcg-op.c471 tcg_debug_assert(arg2 >= 0 && arg2 < 32); in tcg_gen_shli_i32()
486 tcg_debug_assert(arg2 >= 0 && arg2 < 32); in tcg_gen_shri_i32()
501 tcg_debug_assert(arg2 >= 0 && arg2 < 32); in tcg_gen_sari_i32()
836 tcg_debug_assert(arg2 >= 0 && arg2 < 32); in tcg_gen_rotli_i32()
880 tcg_debug_assert(arg2 >= 0 && arg2 < 32); in tcg_gen_rotri_i32()
890 tcg_debug_assert(ofs < 32); in tcg_gen_deposit_i32()
891 tcg_debug_assert(len > 0); in tcg_gen_deposit_i32()
892 tcg_debug_assert(len <= 32); in tcg_gen_deposit_i32()
893 tcg_debug_assert(ofs + len <= 32); in tcg_gen_deposit_i32()
935 tcg_debug_assert(of in tcg_gen_deposit_z_i32()
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H A Dtcg-op-gvec.c47 tcg_debug_assert(oprsz <= maxsz); in check_size_align()
50 tcg_debug_assert(oprsz == maxsz); in check_size_align()
53 tcg_debug_assert(maxsz <= (8 << SIMD_MAXSZ_BITS)); in check_size_align()
56 tcg_debug_assert((maxsz & max_align) == 0); in check_size_align()
57 tcg_debug_assert((ofs & max_align) == 0); in check_size_align()
68 tcg_debug_assert(dbase != abase || d == a || d + s <= a || a + s <= d); in check_overlap_2()
113 tcg_debug_assert(data == sextract32(data, 0, SIMD_DATA_BITS) || in simd_desc()
388 tcg_debug_assert((r & 7) == 0); in check_size_impl()
518 tcg_debug_assert(oprsz >= 8); in do_dup_store()
1781 tcg_debug_assert(vece <= MO_32); in tcg_gen_gvec_dup_i32()
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/openbmc/qemu/include/tcg/
H A Ddebug-assert.h11 # define tcg_debug_assert(X) do { assert(X); } while (0) macro
13 # define tcg_debug_assert(X) \ macro
H A Dtcg.h174 tcg_debug_assert(i < TCG_TYPE_COUNT); in tcg_type_size()
607 tcg_debug_assert(arg < INSN_START_WORDS); in tcg_get_insn_start_param()
618 tcg_debug_assert(arg < INSN_START_WORDS); in tcg_set_insn_start_param()
/openbmc/qemu/tcg/loongarch64/
H A Dtcg-insn-defs.c.inc596 tcg_debug_assert(d >= 0 && d <= 0x1f);
597 tcg_debug_assert(fj >= 0x20 && fj <= 0x3f);
604 tcg_debug_assert(d >= 0 && d <= 0x1f);
605 tcg_debug_assert(j >= 0 && j <= 0x1f);
612 tcg_debug_assert(d >= 0 && d <= 0x1f);
613 tcg_debug_assert(j >= 0 && j <= 0x1f);
614 tcg_debug_assert(k >= 0 && k <= 0x1f);
621 tcg_debug_assert(d >= 0 && d <= 0x1f);
622 tcg_debug_assert(j >= 0 && j <= 0x1f);
623 tcg_debug_assert(sk12 >= -0x800 && sk12 <= 0x7ff);
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/openbmc/qemu/target/arm/tcg/
H A Dgengvec.c32 tcg_debug_assert(opr_sz <= sizeof_field(CPUARMState, vfp.qc)); in gen_gvec_fn3_qc()
44 tcg_debug_assert(vece >= 1 && vece <= 2); in gen_gvec_sqdmulh_qc()
54 tcg_debug_assert(vece >= 1 && vece <= 2); in gen_gvec_sqrdmulh_qc()
64 tcg_debug_assert(vece >= 1 && vece <= 2); in gen_gvec_sqrdmlah_qc()
74 tcg_debug_assert(vece >= 1 && vece <= 2); in gen_gvec_sqrdmlsh_qc()
175 tcg_debug_assert(shift > 0); in gen_gvec_ssra()
176 tcg_debug_assert(shift <= (8 << vece)); in gen_gvec_ssra()
251 tcg_debug_assert(shift > 0); in gen_gvec_usra()
252 tcg_debug_assert(shift <= (8 << vece)); in gen_gvec_usra()
358 tcg_debug_assert(shift > 0); in gen_gvec_srshr()
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H A Dgengvec64.c126 tcg_debug_assert(shift >= 0); in gen_gvec_xar()
127 tcg_debug_assert(shift <= esize); in gen_gvec_xar()
273 tcg_debug_assert(opr_sz <= sizeof_field(CPUARMState, vfp.qc)); in gen_gvec_suqadd_qc()
368 tcg_debug_assert(opr_sz <= sizeof_field(CPUARMState, vfp.qc)); in gen_gvec_usqadd_qc()
/openbmc/qemu/host/include/loongarch64/host/
H A Datomic128-ldst.h.inc27 tcg_debug_assert(HAVE_ATOMIC128_RO);
45 tcg_debug_assert(HAVE_ATOMIC128_RW);
H A Dload-extract-al16-al8.h.inc30 tcg_debug_assert(HAVE_ATOMIC128_RO);
/openbmc/qemu/include/accel/tcg/
H A Dcpu-mmu-index.h38 tcg_debug_assert(ret >= 0 && ret < NB_MMU_MODES); in cpu_mmu_index()
/openbmc/qemu/tcg/tci/
H A Dtcg-target.c.inc70 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL);
71 tcg_debug_assert(slot >= 0 && slot < 128 / TCG_TARGET_REG_BITS);
101 tcg_debug_assert(addend == 0);
102 tcg_debug_assert(type == 20);
114 tcg_debug_assert(offset >= 0);
115 tcg_debug_assert(offset < (TCG_STATIC_CALL_ARGS_SIZE +
139 tcg_debug_assert(diff != 0);
167 tcg_debug_assert(i1 == sextract32(i1, 0, 20));
199 tcg_debug_assert(m2 == extract32(m2, 0, 16));
224 tcg_debug_assert(i
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/openbmc/qemu/tcg/s390x/
H A Dtcg-target.c.inc409 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL);
410 tcg_debug_assert(slot == 0);
743 tcg_debug_assert(is_vector_reg(v1));
752 tcg_debug_assert(is_vector_reg(v1));
761 tcg_debug_assert(is_vector_reg(v1));
762 tcg_debug_assert(is_vector_reg(v3));
771 tcg_debug_assert(is_vector_reg(v1));
772 tcg_debug_assert(is_vector_reg(v2));
780 tcg_debug_assert(is_vector_reg(v1));
781 tcg_debug_assert(is_vector_reg(v2));
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/openbmc/qemu/tcg/ppc/
H A Dtcg-target.c.inc175 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL);
176 tcg_debug_assert(slot >= 0 && slot <= 1);
219 tcg_debug_assert(in_range_b(disp));
239 tcg_debug_assert(disp == (int16_t) disp);
869 tcg_debug_assert(ret >= TCG_REG_V0 && arg >= TCG_REG_V0);
895 tcg_debug_assert((mb & 0x1f) == mb);
896 tcg_debug_assert((me & 0x1f) == me);
986 tcg_debug_assert((imm & 0xffff) == 0);
987 tcg_debug_assert(imm == (int32_t)imm);
1228 tcg_debug_assert(re
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/openbmc/qemu/host/include/aarch64/host/
H A Dload-extract-al16-al8.h.inc35 tcg_debug_assert(HAVE_ATOMIC128_RO);
H A Datomic128-ldst.h.inc32 tcg_debug_assert(HAVE_ATOMIC128_RO);
/openbmc/qemu/target/rx/
H A Dop_helper.c238 tcg_debug_assert(sz < 3); in helper_sstr()
287 tcg_debug_assert(sz < 3); in helper_suntil()
306 tcg_debug_assert(sz < 3); in helper_swhile()
/openbmc/qemu/target/mips/tcg/
H A Dexception.c84 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); in mips_cpu_synchronize_from_tb()
/openbmc/qemu/host/include/x86_64/host/
H A Datomic128-ldst.h.inc37 tcg_debug_assert(HAVE_ATOMIC128_RO);
/openbmc/qemu/tcg/riscv/
H A Dtcg-target.c.inc110 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL);
111 tcg_debug_assert(slot >= 0 && slot <= 1);
614 tcg_debug_assert((offset & 1) == 0);
628 tcg_debug_assert((offset & 1) == 0);
656 tcg_debug_assert(addend == 0);
813 tcg_debug_assert(ret == true);
972 tcg_debug_assert(data >= TCG_REG_V0);
973 tcg_debug_assert(addr < TCG_REG_V0);
976 tcg_debug_assert(addr != TCG_REG_ZERO);
1009 tcg_debug_assert(idx < ARRAY_SIZE(whole_reg_ld));
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