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Searched refs:smu_v11_0_set_hard_freq_limited_range (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/inc/
H A Dsmu_v11_0.h260 int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu,
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dnavi10_ppt.c1854 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq); in navi10_pre_display_config_changed()
2125 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); in navi10_notify_smc_display_config()
2340 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0); in navi10_display_disable_memory_clock_switch()
2342 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0); in navi10_display_disable_memory_clock_switch()
2809 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_min); in navi10_umc_hybrid_cdr_workaround()
2814 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_max); in navi10_umc_hybrid_cdr_workaround()
H A Dsmu_v11_0.c1091 ret = smu_v11_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0); in smu_v11_0_display_clock_voltage_request()
1794 int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu, in smu_v11_0_set_hard_freq_limited_range() function
H A Dsienna_cichlid_ppt.c1538 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq); in sienna_cichlid_pre_display_config_changed()
1810 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); in sienna_cichlid_notify_smc_display_config()
2075 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0); in sienna_cichlid_display_disable_memory_clock_switch()
2077 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0); in sienna_cichlid_display_disable_memory_clock_switch()