Searched refs:riscv_cpu_cfg (Results 1 – 10 of 10) sorted by relevance
95 if (riscv_cpu_cfg(env)->ext_smepmp) { in pmp_write_cfg()277 if (!riscv_cpu_cfg(env)->pmp || (mode == PRV_M)) { in pmp_hart_has_privs_default()322 if (riscv_cpu_cfg(env)->mmu) { in pmp_hart_has_privs()591 if (riscv_cpu_cfg(env)->ext_smepmp) { in mseccfg_csr_write()639 if (!riscv_cpu_cfg(env)->pmp || !pmp_get_num_rules(env)) { in pmp_get_tlb_size()
82 !riscv_cpu_cfg(env)->ext_zfinx) { in fs()95 if (riscv_cpu_cfg(env)->ext_zve32x) { in vs()173 if (!riscv_cpu_cfg(env)->ext_zcmt) { in zcmt()545 if (riscv_cpu_cfg(env)->pmp) { in pmp()566 if (riscv_cpu_cfg(env)->ext_zkr) { in have_mseccfg()575 if (riscv_cpu_cfg(env)->debug) { in debug()585 if (!riscv_cpu_cfg(env)->ext_zkr) { in seed()713 *val = riscv_cpu_cfg(env)->vlenb; in read_vlenb()1465 *val = riscv_cpu_cfg(env)->mimpid; in read_mimpid()3305 if (!riscv_cpu_cfg(env)->mmu) { in read_satp()[all …]
356 if (!((extirq == IRQ_M_EXT) ? riscv_cpu_cfg(env)->ext_smaia : in riscv_cpu_pending_to_irq()357 riscv_cpu_cfg(env)->ext_ssaia)) { in riscv_cpu_pending_to_irq()763 if (!riscv_cpu_cfg(env)->pmp) { in get_physical_address_pmp()833 if (mode == PRV_M || !riscv_cpu_cfg(env)->mmu) { in get_physical_address()914 bool svade = riscv_cpu_cfg(env)->ext_svade; in get_physical_address()915 bool svadu = riscv_cpu_cfg(env)->ext_svadu; in get_physical_address()994 if (!riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { in get_physical_address()1149 if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { in get_physical_address()
221 if (!riscv_cpu_cfg(env)->mmu) { in hmp_info_mem()
329 if (riscv_cpu_cfg(env)->pmp && in helper_mret()
630 static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) in riscv_cpu_cfg() function
584 uint32_t vlenb = riscv_cpu_cfg(env)->vlenb; in GEN_VEXT_LDFF()964 uint32_t total_elems = riscv_cpu_cfg(env)->vlenb << 3; \1004 uint32_t total_elems = riscv_cpu_cfg(env)->vlenb << 3; \1214 uint32_t total_elems = riscv_cpu_cfg(env)->vlenb << 3; \1281 uint32_t total_elems = riscv_cpu_cfg(env)->vlenb << 3; \4036 uint32_t total_elems = riscv_cpu_cfg(env)->vlenb << 3; \ in RVVCALL()4078 uint32_t total_elems = riscv_cpu_cfg(env)->vlenb << 3; \4599 uint32_t total_elems = riscv_cpu_cfg(env)->vlenb << 3;\ in GEN_VEXT_FRED()4688 uint32_t total_elems = riscv_cpu_cfg(env)->vlenb << 3; in vmsetm()
1010 if (riscv_cpu_cfg(env)->ext_smepmp) { in riscv_cpu_reset_hold()
14 const RISCVCPUConfig *cfg = riscv_cpu_cfg((CPURISCVState *) cpu_env); in open_cpuinfo()
8881 const RISCVCPUConfig *cfg = riscv_cpu_cfg(env); in risc_hwprobe_fill_pairs()