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Searched refs:regUVD_MPC_SET_MUXA1_BASE_IDX (Results 1 – 3 of 3) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h1045 #define regUVD_MPC_SET_MUXA1_BASE_IDX … macro
H A Dvcn_4_0_0_offset.h461 #define regUVD_MPC_SET_MUXA1_BASE_IDX … macro
H A Dvcn_4_0_3_offset.h463 #define regUVD_MPC_SET_MUXA1_BASE_IDX … macro