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Searched refs:regSQC_DCACHE_UTCL1_CNTL2_BASE_IDX (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h6393 #define regSQC_DCACHE_UTCL1_CNTL2_BASE_IDX … macro
H A Dgc_9_4_3_offset.h703 #define regSQC_DCACHE_UTCL1_CNTL2_BASE_IDX … macro