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Searched refs:regOTG0_OTG_DRR_CONTROL (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_2_offset.h8949 #define regOTG0_OTG_DRR_CONTROL … macro
H A Ddcn_3_1_5_offset.h8710 #define regOTG0_OTG_DRR_CONTROL … macro
H A Ddcn_3_1_4_offset.h8006 #define regOTG0_OTG_DRR_CONTROL … macro
H A Ddcn_3_2_1_offset.h8080 #define regOTG0_OTG_DRR_CONTROL … macro
H A Ddcn_3_2_0_offset.h8081 #define regOTG0_OTG_DRR_CONTROL … macro
H A Ddcn_3_1_6_offset.h9173 #define regOTG0_OTG_DRR_CONTROL … macro