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Searched refs:regGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h852 #define regGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX … macro
H A Dgc_9_4_3_offset.h1205 #define regGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX … macro
H A Dgc_11_0_0_offset.h2457 #define regGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX … macro
H A Dgc_11_0_3_offset.h2565 #define regGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX … macro