Home
last modified time | relevance | path

Searched refs:regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_2_offset.h12490 #define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h12355 #define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h11619 #define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h11723 #define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX … macro
H A Ddcn_3_2_0_offset.h11714 #define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h13086 #define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX … macro