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Searched refs:regCP_CPC_IC_BASE_LO (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c2142 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, in gfx_v11_0_config_mec_cache()
2430 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, addr); in gfx_v11_0_config_mec_cache_rs64()
3518 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr); in gfx_v11_0_cp_compute_load_microcode_rs64()
H A Dgfx_v9_4_3.c1420 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO, in gfx_v9_4_3_xcc_cp_compute_load_microcode()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h581 #define regCP_CPC_IC_BASE_LO … macro
H A Dgc_9_4_3_offset.h3042 #define regCP_CPC_IC_BASE_LO … macro
H A Dgc_11_0_0_offset.h9726 #define regCP_CPC_IC_BASE_LO … macro
H A Dgc_11_0_3_offset.h10286 #define regCP_CPC_IC_BASE_LO … macro