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/openbmc/qemu/hw/riscv/
H A Driscv-iommu.c1853 uint32_t cqcsr, fqcsr, pqcsr; in riscv_iommu_update_ipsr() local
1888 pqcsr = riscv_iommu_reg_get32(s, RISCV_IOMMU_REG_PQCSR); in riscv_iommu_update_ipsr()
1890 if (pqcsr & RISCV_IOMMU_PQCSR_PIE && in riscv_iommu_update_ipsr()
1891 (pqcsr & RISCV_IOMMU_PQCSR_PQOF || in riscv_iommu_update_ipsr()
1892 pqcsr & RISCV_IOMMU_PQCSR_PQMF)) { in riscv_iommu_update_ipsr()