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Searched refs:pci_dev (Results 1 – 25 of 110) sorted by relevance

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/openbmc/qemu/hw/pci/
H A Dpci_host.c65 static bool is_pci_dev_ejected(PCIDevice *pci_dev) in is_pci_dev_ejected() argument
72 return pci_dev && pci_dev->partially_hotplugged && in is_pci_dev_ejected()
73 !pci_dev->qdev.pending_deleted_event; in is_pci_dev_ejected()
76 void pci_host_config_write_common(PCIDevice *pci_dev, uint32_t addr, in pci_host_config_write_common() argument
79 pci_adjust_config_limit(pci_get_bus(pci_dev), &limit); in pci_host_config_write_common()
88 if ((pci_dev->qdev.hotplugged && !pci_get_function_0(pci_dev)) || in pci_host_config_write_common()
89 !pci_dev->enabled || is_pci_dev_ejected(pci_dev)) { in pci_host_config_write_common()
93 trace_pci_cfg_write(pci_dev->name, pci_dev_bus_num(pci_dev), in pci_host_config_write_common()
94 PCI_SLOT(pci_dev->devfn), in pci_host_config_write_common()
95 PCI_FUNC(pci_dev->devfn), addr, val); in pci_host_config_write_common()
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H A Dpci.c138 static void pci_init_bus_master(PCIDevice *pci_dev) in pci_init_bus_master() argument
140 AddressSpace *dma_as = pci_device_iommu_address_space(pci_dev); in pci_init_bus_master()
142 memory_region_init_alias(&pci_dev->bus_master_enable_region, in pci_init_bus_master()
143 OBJECT(pci_dev), "bus master", in pci_init_bus_master()
145 pci_set_master(pci_dev, false); in pci_init_bus_master()
146 memory_region_add_subregion(&pci_dev->bus_master_container_region, 0, in pci_init_bus_master()
147 &pci_dev->bus_master_enable_region); in pci_init_bus_master()
375 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) in pci_change_irq_level() argument
380 bus = pci_get_bus(pci_dev); in pci_change_irq_level()
382 irq_num = bus->map_irq(pci_dev, irq_nu in pci_change_irq_level()
943 pci_set_default_subsystem_id(PCIDevice * pci_dev) pci_set_default_subsystem_id() argument
1163 pci_config_alloc(PCIDevice * pci_dev) pci_config_alloc() argument
1174 pci_config_free(PCIDevice * pci_dev) pci_config_free() argument
1183 do_pci_unregister_device(PCIDevice * pci_dev) do_pci_unregister_device() argument
1299 do_pci_register_device(PCIDevice * pci_dev,const char * name,int devfn,Error ** errp) do_pci_register_device() argument
1420 pci_unregister_io_regions(PCIDevice * pci_dev) pci_unregister_io_regions() argument
1437 PCIDevice *pci_dev = PCI_DEVICE(dev); pci_qdev_unrealize() local
1465 pci_register_bar(PCIDevice * pci_dev,int region_num,uint8_t type,MemoryRegion * memory) pci_register_bar() argument
1521 pci_update_vga(PCIDevice * pci_dev) pci_update_vga() argument
1539 pci_register_vga(PCIDevice * pci_dev,MemoryRegion * mem,MemoryRegion * io_lo,MemoryRegion * io_hi) pci_register_vga() argument
1565 pci_unregister_vga(PCIDevice * pci_dev) pci_unregister_vga() argument
1582 pci_get_bar_addr(PCIDevice * pci_dev,int region_num) pci_get_bar_addr() argument
1812 PCIDevice *pci_dev = opaque; pci_irq_handler() local
1828 pci_allocate_irq(PCIDevice * pci_dev) pci_allocate_irq() argument
1836 pci_set_irq(PCIDevice * pci_dev,int level) pci_set_irq() argument
1914 pci_swizzle_map_irq_fn(PCIDevice * pci_dev,int pin) pci_swizzle_map_irq_fn() argument
2052 PCIDevice *pci_dev; pci_init_nic_in_slot() local
2215 PCIDevice *pci_dev = (PCIDevice *)qdev; pci_qdev_realize() local
3239 pci_get_function_0(PCIDevice * pci_dev) pci_get_function_0() argument
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H A Dpcie_host.c40 PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, mmcfg_addr); in pcie_mmcfg_data_write() local
44 if (!pci_dev) { in pcie_mmcfg_data_write()
48 limit = pci_config_size(pci_dev); in pcie_mmcfg_data_write()
49 pci_host_config_write_common(pci_dev, addr, limit, val, len); in pcie_mmcfg_data_write()
58 PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, mmcfg_addr); in pcie_mmcfg_data_read() local
62 if (!pci_dev) { in pcie_mmcfg_data_read()
66 limit = pci_config_size(pci_dev); in pcie_mmcfg_data_read()
67 return pci_host_config_read_common(pci_dev, addr, limit, len); in pcie_mmcfg_data_read()
/openbmc/qemu/hw/remote/
H A Dvfio-user-obj.c110 PCIDevice *pci_dev;
212 g_assert(o->pci_dev); in vfu_object_ctx_run()
213 pci_dev_path = object_get_canonical_path(OBJECT(o->pci_dev)); in vfu_object_ctx_run()
290 pci_host_config_write_common(o->pci_dev, offset, in vfu_object_cfg_access()
291 pci_config_size(o->pci_dev), in vfu_object_cfg_access()
295 val = pci_host_config_read_common(o->pci_dev, offset, in vfu_object_cfg_access()
296 pci_config_size(o->pci_dev), len); in vfu_object_cfg_access()
328 dma_as = pci_device_iommu_address_space(o->pci_dev); in dma_register()
347 dma_as = pci_device_iommu_address_space(o->pci_dev); in dma_unregister()
424 static size_t vfu_object_bar_rw(PCIDevice *pci_dev, in in vfu_object_bar_rw()
105 PCIDevice *pci_dev; global() member
419 vfu_object_bar_rw(PCIDevice * pci_dev,int pci_bar,hwaddr bar_offset,char * const buf,hwaddr len,const bool is_write) vfu_object_bar_rw() argument
538 vfu_object_map_irq(PCIDevice * pci_dev,int intx) vfu_object_map_irq() argument
549 PCIDevice *pci_dev = NULL; vfu_object_set_irq() local
573 vfu_object_msi_prepare_msg(PCIDevice * pci_dev,unsigned int vector) vfu_object_msi_prepare_msg() argument
584 vfu_object_msi_trigger(PCIDevice * pci_dev,MSIMessage msg) vfu_object_msi_trigger() argument
638 vfu_object_setup_irqs(VfuObject * o,PCIDevice * pci_dev) vfu_object_setup_irqs() argument
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H A Diohub.c36 int remote_iohub_map_irq(PCIDevice *pci_dev, int intx) in remote_iohub_map_irq() argument
38 return pci_dev->devfn; in remote_iohub_map_irq()
78 void process_set_irqfd_msg(PCIDevice *pci_dev, MPQemuMsg *msg) in process_set_irqfd_msg() argument
84 intx = pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1; in process_set_irqfd_msg()
86 pirq = remote_iohub_map_irq(pci_dev, intx); in process_set_irqfd_msg()
H A Dmessage.c35 PCIDevice *pci_dev = NULL; in mpqemu_remote_msg_loop_co() local
40 pci_dev = com->dev; in mpqemu_remote_msg_loop_co()
57 process_config_write(com->ioc, pci_dev, &msg, &local_err); in mpqemu_remote_msg_loop_co()
60 process_config_read(com->ioc, pci_dev, &msg, &local_err); in mpqemu_remote_msg_loop_co()
72 process_set_irqfd_msg(pci_dev, &msg); in mpqemu_remote_msg_loop_co()
75 process_device_reset_msg(com->ioc, pci_dev, &local_err); in mpqemu_remote_msg_loop_co()
81 msg.cmd, DEVICE(pci_dev)->id, getpid()); in mpqemu_remote_msg_loop_co()
/openbmc/qemu/hw/usb/
H A Dhcd-xhci-pci.c41 PCIDevice *pci_dev = PCI_DEVICE(s); in xhci_pci_intr_update() local
43 if (!msix_enabled(pci_dev)) { in xhci_pci_intr_update()
51 msix_vector_use(pci_dev, n); in xhci_pci_intr_update()
55 msix_vector_unuse(pci_dev, n); in xhci_pci_intr_update()
63 PCIDevice *pci_dev = PCI_DEVICE(s); in xhci_pci_intr_raise() local
66 !(msix_enabled(pci_dev) || in xhci_pci_intr_raise()
67 msi_enabled(pci_dev))) { in xhci_pci_intr_raise()
68 pci_set_irq(pci_dev, level); in xhci_pci_intr_raise()
71 if (msix_enabled(pci_dev) && level) { in xhci_pci_intr_raise()
72 msix_notify(pci_dev, n); in xhci_pci_intr_raise()
[all …]
/openbmc/qemu/hw/net/
H A Dne2000-pci.c55 static void pci_ne2000_realize(PCIDevice *pci_dev, Error **errp) in pci_ne2000_realize() argument
57 PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev); in pci_ne2000_realize()
65 ne2000_setup_io(s, DEVICE(pci_dev), 0x100); in pci_ne2000_realize()
73 object_get_typename(OBJECT(pci_dev)), in pci_ne2000_realize()
74 pci_dev->qdev.id, in pci_ne2000_realize()
75 &pci_dev->qdev.mem_reentrancy_guard, s); in pci_ne2000_realize()
79 static void pci_ne2000_exit(PCIDevice *pci_dev) in pci_ne2000_exit() argument
81 PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev); in pci_ne2000_exit()
90 PCIDevice *pci_dev = PCI_DEVICE(obj); in ne2000_instance_init() local
91 PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev); in ne2000_instance_init()
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H A Digb.c321 igb_init_net_peer(IGBState *s, PCIDevice *pci_dev, uint8_t *macaddr) in igb_init_net_peer() argument
323 DeviceState *dev = DEVICE(pci_dev); in igb_init_net_peer()
381 static void igb_pci_realize(PCIDevice *pci_dev, Error **errp) in igb_pci_realize() argument
383 IGBState *s = IGB(pci_dev); in igb_pci_realize()
389 pci_dev->config_write = igb_write_config; in igb_pci_realize()
391 pci_dev->config[PCI_CACHE_LINE_SIZE] = 0x10; in igb_pci_realize()
392 pci_dev->config[PCI_INTERRUPT_PIN] = 1; in igb_pci_realize()
397 pci_register_bar(pci_dev, E1000E_MMIO_IDX, in igb_pci_realize()
406 pci_register_bar(pci_dev, E1000E_FLASH_IDX, in igb_pci_realize()
411 pci_register_bar(pci_dev, E1000E_IO_IDX, in igb_pci_realize()
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H A De1000e.c316 e1000e_init_net_peer(E1000EState *s, PCIDevice *pci_dev, uint8_t *macaddr) in e1000e_init_net_peer() argument
318 DeviceState *dev = DEVICE(pci_dev); in e1000e_init_net_peer()
397 static void e1000e_write_config(PCIDevice *pci_dev, uint32_t address, in e1000e_write_config() argument
400 E1000EState *s = E1000E(pci_dev); in e1000e_write_config()
402 pci_default_write_config(pci_dev, address, val, len); in e1000e_write_config()
405 (pci_dev->config[PCI_COMMAND] & PCI_COMMAND_MASTER)) { in e1000e_write_config()
410 static void e1000e_pci_realize(PCIDevice *pci_dev, Error **errp) in e1000e_pci_realize() argument
416 E1000EState *s = E1000E(pci_dev); in e1000e_pci_realize()
422 pci_dev->config_write = e1000e_write_config; in e1000e_pci_realize()
424 pci_dev->config[PCI_CACHE_LINE_SIZE] = 0x10; in e1000e_pci_realize()
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H A Dpcnet-pci.c197 static void pci_pcnet_realize(PCIDevice *pci_dev, Error **errp) in pci_pcnet_realize() argument
199 PCIPCNetState *d = PCI_PCNET(pci_dev); in pci_pcnet_realize()
208 pci_conf = pci_dev->config; in pci_pcnet_realize()
226 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->io_bar); in pci_pcnet_realize()
228 pci_register_bar(pci_dev, 1, 0, &s->mmio); in pci_pcnet_realize()
230 s->irq = pci_allocate_irq(pci_dev); in pci_pcnet_realize()
233 s->dma_opaque = DEVICE(pci_dev); in pci_pcnet_realize()
235 pcnet_common_init(DEVICE(pci_dev), s, &net_pci_pcnet_info); in pci_pcnet_realize()
/openbmc/qemu/hw/cxl/
H A Dswitch-mailbox-cci.c28 static void cswbcci_realize(PCIDevice *pci_dev, Error **errp) in cswbcci_realize() argument
30 CSWMBCCIDev *cswmb = CXL_SWITCH_MAILBOX_CCI(pci_dev); in cswbcci_realize()
42 pcie_endpoint_cap_init(pci_dev, 0x80); in cswbcci_realize()
44 cxl_cstate->pdev = pci_dev; in cswbcci_realize()
46 cxl_device_register_block_init(OBJECT(pci_dev), cxl_dstate, cswmb->cci); in cswbcci_realize()
47 pci_register_bar(pci_dev, 0, in cswbcci_realize()
60 cxl_initialize_mailbox_swcci(cswmb->cci, DEVICE(pci_dev), in cswbcci_realize()
65 static void cswmbcci_exit(PCIDevice *pci_dev) in cswmbcci_exit() argument
/openbmc/qemu/tests/qtest/libqos/
H A De1000e.c45 qtest_memwrite(d_pci->pci_dev.bus->qts, in e1000e_tx_ring_push()
51 qtest_memread(d_pci->pci_dev.bus->qts, in e1000e_tx_ring_push()
62 qtest_memwrite(d_pci->pci_dev.bus->qts, in e1000e_rx_ring_push()
68 qtest_memread(d_pci->pci_dev.bus->qts, in e1000e_rx_ring_push()
86 if (qpci_msix_pending(&d_pci->pci_dev, msg_id)) { in e1000e_wait_isr()
89 qtest_clock_step(d_pci->pci_dev.bus->qts, 10000); in e1000e_wait_isr()
98 qpci_iounmap(&epci->pci_dev, epci->mac_regs); in e1000e_pci_destructor()
99 qpci_msix_disable(&epci->pci_dev); in e1000e_pci_destructor()
108 qpci_device_enable(&d->pci_dev); in e1000e_pci_start_hw()
115 qpci_msix_enable(&d->pci_dev); in e1000e_pci_start_hw()
[all …]
H A Digb.c50 qpci_iounmap(&epci->pci_dev, epci->mac_regs); in e1000e_pci_destructor()
51 qpci_msix_disable(&epci->pci_dev); in e1000e_pci_destructor()
61 qpci_device_enable(&d->pci_dev); in igb_pci_start_hw()
74 qtest_clock_step(d->pci_dev.bus->qts, 900000000); in igb_pci_start_hw()
77 qpci_msix_enable(&d->pci_dev); in igb_pci_start_hw()
137 return &epci->pci_dev; in igb_pci_get_driver()
151 e1000e_foreach_callback, &d->pci_dev); in igb_pci_create()
154 d->mac_regs = qpci_iomap(&d->pci_dev, 0, NULL); in igb_pci_create()
H A De1000e.h40 QPCIDevice pci_dev; member
48 qpci_io_writel(&d_pci->pci_dev, d_pci->mac_regs, reg, val); in e1000e_macreg_write()
54 return qpci_io_readl(&d_pci->pci_dev, d_pci->mac_regs, reg); in e1000e_macreg_read()
/openbmc/qemu/hw/virtio/
H A Dvirtio-pci.c62 return container_of(d, VirtIOPCIProxy, pci_dev.qdev); in to_virtio_pci_proxy()
70 return container_of(d, VirtIOPCIProxy, pci_dev.qdev); in to_virtio_pci_proxy_fast()
77 if (msix_enabled(&proxy->pci_dev)) { in virtio_pci_notify()
79 msix_notify(&proxy->pci_dev, vector); in virtio_pci_notify()
83 pci_set_irq(&proxy->pci_dev, qatomic_read(&vdev->isr) & 1); in virtio_pci_notify()
92 pci_device_save(&proxy->pci_dev, f); in virtio_pci_save_config()
93 msix_save(&proxy->pci_dev, f); in virtio_pci_save_config()
94 if (msix_present(&proxy->pci_dev)) in virtio_pci_save_config()
217 if (msix_present(&proxy->pci_dev)) in virtio_pci_load_queue()
228 ret = pci_device_load(&proxy->pci_dev,
717 virtio_pci_ats_ctrl_trigger(PCIDevice * pci_dev,bool enable) virtio_pci_ats_ctrl_trigger() argument
749 virtio_write_config(PCIDevice * pci_dev,uint32_t address,uint32_t val,int len) virtio_write_config() argument
794 virtio_read_config(PCIDevice * pci_dev,uint32_t address,int len) virtio_read_config() argument
2150 virtio_pci_realize(PCIDevice * pci_dev,Error ** errp) virtio_pci_realize() argument
2286 virtio_pci_exit(PCIDevice * pci_dev) virtio_pci_exit() argument
2398 PCIDevice *pci_dev = &proxy->pci_dev; virtio_pci_dc_realize() local
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/openbmc/qemu/hw/ide/
H A Dcmd646.c93 PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev); in bmdma_read() local
105 val = pci_dev->config[MRDMODE]; in bmdma_read()
111 if (bm == &bm->pci_dev->bmdma[0]) { in bmdma_read()
112 val = pci_dev->config[UDIDETCR0]; in bmdma_read()
114 val = pci_dev->config[UDIDETCR1]; in bmdma_read()
130 PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev); in bmdma_write() local
142 pci_dev->config[MRDMODE] = in bmdma_write()
143 (pci_dev->config[MRDMODE] & ~0x30) | (val & 0x30); in bmdma_write()
144 cmd646_update_dma_interrupts(pci_dev); in bmdma_write()
145 cmd646_update_irq(pci_dev); in bmdma_write()
[all …]
/openbmc/qemu/hw/pci-host/
H A Dsabre.c272 static int pci_sabre_map_irq(PCIDevice *pci_dev, int irq_num) in pci_sabre_map_irq() argument
278 static int pci_simbaA_map_irq(PCIDevice *pci_dev, int irq_num) in pci_simbaA_map_irq() argument
281 switch (PCI_SLOT(pci_dev->devfn)) { in pci_simbaA_map_irq()
293 return ((PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f; in pci_simbaA_map_irq()
296 static int pci_simbaB_map_irq(PCIDevice *pci_dev, int irq_num) in pci_simbaB_map_irq() argument
298 return (0x10 + (PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f; in pci_simbaB_map_irq()
335 PCIDevice *pci_dev; in sabre_reset() local
358 pci_dev = PCI_DEVICE(s->bridgeA); in sabre_reset()
359 cmd = pci_get_word(pci_dev->config + PCI_COMMAND); in sabre_reset()
360 pci_set_word(pci_dev->config + PCI_COMMAND, cmd | PCI_COMMAND_IO); in sabre_reset()
[all …]
H A Draven.c178 static int raven_map_irq(PCIDevice *pci_dev, int irq_num) in raven_io_write()
180 return (irq_num + (pci_dev->devfn >> 3)) & 1; in raven_io_write()
68 RavenPCIState pci_dev; global() member
197 raven_map_irq(PCIDevice * pci_dev,int irq_num) raven_map_irq() argument
280 DeviceState *pci_dev; raven_pcihost_initfn() local
/openbmc/qemu/hw/mips/
H A Dfuloong2e.c222 PCIDevice *pci_dev; in mips_fuloong2e_init()
289 pci_dev = pci_new_multifunction(PCI_DEVFN(FULOONG2E_VIA_SLOT, 0), in mips_fuloong2e_init()
294 dev = DEVICE(object_resolve_path_component(OBJECT(pci_dev), "ac97")); in mips_fuloong2e_init()
298 pci_realize_and_unref(pci_dev, pci_bus, &error_abort); in mips_fuloong2e_init()
301 object_resolve_path_component(OBJECT(pci_dev), in mips_fuloong2e_init()
304 qdev_connect_gpio_out_named(DEVICE(pci_dev), "intr", 0, env->irq[5]); in mips_fuloong2e_init()
306 dev = DEVICE(object_resolve_path_component(OBJECT(pci_dev), "ide")); in mips_fuloong2e_init()
309 dev = DEVICE(object_resolve_path_component(OBJECT(pci_dev), "pm")); in mips_fuloong2e_init()
315 pci_dev = pci_new(-1, "ati-vga"); in mips_fuloong2e_init()
316 dev = DEVICE(pci_dev); in mips_fuloong2e_init()
221 PCIDevice *pci_dev; mips_fuloong2e_init() local
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/openbmc/qemu/include/hw/pci/
H A Dpci.h146 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
148 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
150 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
152 typedef void PCIUnregisterFunc(PCIDevice *pci_dev);
255 void pci_register_bar(PCIDevice *pci_dev, int region_num,
257 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
259 void pci_unregister_vga(PCIDevice *pci_dev);
260 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
266 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
268 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_
999 pci_irq_assert(PCIDevice * pci_dev) pci_irq_assert() argument
1004 pci_irq_deassert(PCIDevice * pci_dev) pci_irq_deassert() argument
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/openbmc/qemu/hw/sparc64/
H A Dsun4u.c297 static void ebus_realize(PCIDevice *pci_dev, Error **errp) in ebus_realize()
299 EbusState *s = EBUS(pci_dev); in ebus_realize()
306 s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(), in ebus_realize()
307 pci_address_space_io(pci_dev), errp); in ebus_realize()
322 serial_mm_init(pci_address_space(pci_dev), s->console_serial_base, in ebus_realize()
348 memory_region_add_subregion(pci_address_space_io(pci_dev), 0x7240, in ebus_realize()
352 pci_dev->config[0x04] = 0x06; // command = bus master, pci mem in ebus_realize()
353 pci_dev->config[0x05] = 0x00; in ebus_realize()
354 pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error in ebus_realize()
355 pci_dev in ebus_realize()
296 ebus_realize(PCIDevice * pci_dev,Error ** errp) ebus_realize() argument
553 PCIDevice *ebus, *pci_dev; sun4uv_init() local
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/openbmc/qemu/hw/pci-bridge/
H A Dcxl_root_port.c149 PCIDevice *pci_dev = PCI_DEVICE(dev); in cxl_rp_realize() local
164 pci_bridge_qemu_reserve_cap_init(pci_dev, 0, crp->res_reserve, errp); in cxl_rp_realize()
166 rpc->parent_class.exit(pci_dev); in cxl_rp_realize()
171 pci_word_test_and_clear_mask(pci_dev->wmask + PCI_COMMAND, in cxl_rp_realize()
173 pci_dev->wmask[PCI_IO_BASE] = 0; in cxl_rp_realize()
174 pci_dev->wmask[PCI_IO_LIMIT] = 0; in cxl_rp_realize()
178 cxl_cstate->pdev = pci_dev; in cxl_rp_realize()
181 cxl_component_register_block_init(OBJECT(pci_dev), cxl_cstate, in cxl_rp_realize()
184 pci_register_bar(pci_dev, CXL_COMPONENT_REG_BAR_IDX, in cxl_rp_realize()
/openbmc/qemu/include/hw/xen/
H A Dxen_native.h436 PCIDevice *pci_dev) in xen_map_pcidev() argument
442 trace_xen_map_pcidev(ioservid, pci_dev_bus_num(pci_dev), in xen_map_pcidev()
443 PCI_SLOT(pci_dev->devfn), PCI_FUNC(pci_dev->devfn)); in xen_map_pcidev()
445 pci_dev_bus_num(pci_dev), in xen_map_pcidev()
446 PCI_SLOT(pci_dev->devfn), in xen_map_pcidev()
447 PCI_FUNC(pci_dev->devfn)); in xen_map_pcidev()
452 PCIDevice *pci_dev) in xen_unmap_pcidev() argument
458 trace_xen_unmap_pcidev(ioservid, pci_dev_bus_num(pci_dev), in xen_unmap_pcidev()
459 PCI_SLOT(pci_dev->devfn), PCI_FUNC(pci_dev->devfn)); in xen_unmap_pcidev()
461 pci_dev_bus_num(pci_dev), in xen_unmap_pcidev()
[all …]
/openbmc/qemu/hw/i386/xen/
H A Dxen_pvdevice.c86 static void xen_pv_realize(PCIDevice *pci_dev, Error **errp) in xen_pv_realize() argument
88 XenPVDevice *d = XEN_PV_DEVICE(pci_dev); in xen_pv_realize()
97 pci_conf = pci_dev->config; in xen_pv_realize()
114 pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_MEM_PREFETCH, in xen_pv_realize()

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