Searched refs:mvien (Results 1 – 4 of 4) sorted by relevance
410 uint64_t irqs_f = env->mvip & env->mvien & ~env->mideleg & env->sie; in riscv_cpu_sirq_pending()462 irqs_f = env->mvip & (env->mvien & ~env->mideleg) & env->sie; in riscv_cpu_local_irq_pending()645 irqf = env->mvien & env->mvip & env->sie; in riscv_cpu_interrupt()1665 bool s_injected = env->mvip & (1 << cause) & env->mvien && in riscv_cpu_do_interrupt()
1851 *ret_val = env->mvien; in rmw_mvien64()1854 env->mvien = (env->mvien & ~mask) | (new_val & mask); in rmw_mvien64()2034 if (env->priv == PRV_S && env->mvien & MIP_SEIP && in rmw_xireg()2106 if (env->mvien & MIP_SEIP && env->priv == PRV_S) { in rmw_xtopei()2791 (env->mideleg | ~env->mvien)) | MIP_STIP; in rmw_mvip64()2793 (~env->mideleg & env->mvien); in rmw_mvip64()2808 alias_mask &= (env->mideleg | env->mvien); in rmw_mvip64()2809 nalias_mask &= (env->mideleg | env->mvien); in rmw_mvip64()3005 (~env->mideleg & env->mvien); in rmw_sie64()3251 uint64_t mask = (env->mideleg | env->mvien) & sip_writable_mask; in rmw_sip64()[all …]
383 VMSTATE_UINT64(env.mvien, RISCVCPU),
298 uint64_t mvien; member