/openbmc/linux/drivers/gpu/drm/amd/amdgpu/ |
H A D | cik_ih.c | 392 tmp = RREG32(mmSRBM_SOFT_RESET); in cik_ih_soft_reset() 395 WREG32(mmSRBM_SOFT_RESET, tmp); in cik_ih_soft_reset() 396 tmp = RREG32(mmSRBM_SOFT_RESET); in cik_ih_soft_reset() 401 WREG32(mmSRBM_SOFT_RESET, tmp); in cik_ih_soft_reset() 402 tmp = RREG32(mmSRBM_SOFT_RESET); in cik_ih_soft_reset()
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H A D | iceland_ih.c | 382 tmp = RREG32(mmSRBM_SOFT_RESET); in iceland_ih_soft_reset() 385 WREG32(mmSRBM_SOFT_RESET, tmp); in iceland_ih_soft_reset() 386 tmp = RREG32(mmSRBM_SOFT_RESET); in iceland_ih_soft_reset() 391 WREG32(mmSRBM_SOFT_RESET, tmp); in iceland_ih_soft_reset() 392 tmp = RREG32(mmSRBM_SOFT_RESET); in iceland_ih_soft_reset()
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H A D | cz_ih.c | 388 tmp = RREG32(mmSRBM_SOFT_RESET); in cz_ih_soft_reset() 391 WREG32(mmSRBM_SOFT_RESET, tmp); in cz_ih_soft_reset() 392 tmp = RREG32(mmSRBM_SOFT_RESET); in cz_ih_soft_reset() 397 WREG32(mmSRBM_SOFT_RESET, tmp); in cz_ih_soft_reset() 398 tmp = RREG32(mmSRBM_SOFT_RESET); in cz_ih_soft_reset()
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H A D | tonga_ih.c | 440 tmp = RREG32(mmSRBM_SOFT_RESET); in tonga_ih_soft_reset() 443 WREG32(mmSRBM_SOFT_RESET, tmp); in tonga_ih_soft_reset() 444 tmp = RREG32(mmSRBM_SOFT_RESET); in tonga_ih_soft_reset() 449 WREG32(mmSRBM_SOFT_RESET, tmp); in tonga_ih_soft_reset() 450 tmp = RREG32(mmSRBM_SOFT_RESET); in tonga_ih_soft_reset()
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H A D | gmc_v6_0.c | 1002 tmp = RREG32(mmSRBM_SOFT_RESET); in gmc_v6_0_soft_reset() 1005 WREG32(mmSRBM_SOFT_RESET, tmp); in gmc_v6_0_soft_reset() 1006 tmp = RREG32(mmSRBM_SOFT_RESET); in gmc_v6_0_soft_reset() 1011 WREG32(mmSRBM_SOFT_RESET, tmp); in gmc_v6_0_soft_reset() 1012 tmp = RREG32(mmSRBM_SOFT_RESET); in gmc_v6_0_soft_reset()
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H A D | vce_v3_0.c | 685 tmp = RREG32(mmSRBM_SOFT_RESET); in vce_v3_0_soft_reset() 688 WREG32(mmSRBM_SOFT_RESET, tmp); in vce_v3_0_soft_reset() 689 tmp = RREG32(mmSRBM_SOFT_RESET); in vce_v3_0_soft_reset() 694 WREG32(mmSRBM_SOFT_RESET, tmp); in vce_v3_0_soft_reset() 695 tmp = RREG32(mmSRBM_SOFT_RESET); in vce_v3_0_soft_reset()
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H A D | sdma_v2_4.c | 976 tmp = RREG32(mmSRBM_SOFT_RESET); in sdma_v2_4_soft_reset() 979 WREG32(mmSRBM_SOFT_RESET, tmp); in sdma_v2_4_soft_reset() 980 tmp = RREG32(mmSRBM_SOFT_RESET); in sdma_v2_4_soft_reset() 985 WREG32(mmSRBM_SOFT_RESET, tmp); in sdma_v2_4_soft_reset() 986 tmp = RREG32(mmSRBM_SOFT_RESET); in sdma_v2_4_soft_reset()
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H A D | gmc_v7_0.c | 1198 tmp = RREG32(mmSRBM_SOFT_RESET); in gmc_v7_0_soft_reset() 1201 WREG32(mmSRBM_SOFT_RESET, tmp); in gmc_v7_0_soft_reset() 1202 tmp = RREG32(mmSRBM_SOFT_RESET); in gmc_v7_0_soft_reset() 1207 WREG32(mmSRBM_SOFT_RESET, tmp); in gmc_v7_0_soft_reset() 1208 tmp = RREG32(mmSRBM_SOFT_RESET); in gmc_v7_0_soft_reset()
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H A D | cik_sdma.c | 1083 tmp = RREG32(mmSRBM_SOFT_RESET); in cik_sdma_soft_reset() 1086 WREG32(mmSRBM_SOFT_RESET, tmp); in cik_sdma_soft_reset() 1087 tmp = RREG32(mmSRBM_SOFT_RESET); in cik_sdma_soft_reset() 1092 WREG32(mmSRBM_SOFT_RESET, tmp); in cik_sdma_soft_reset() 1093 tmp = RREG32(mmSRBM_SOFT_RESET); in cik_sdma_soft_reset()
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H A D | vce_v4_0.c | 782 tmp = RREG32(mmSRBM_SOFT_RESET); 785 WREG32(mmSRBM_SOFT_RESET, tmp); 786 tmp = RREG32(mmSRBM_SOFT_RESET); 791 WREG32(mmSRBM_SOFT_RESET, tmp); 792 tmp = RREG32(mmSRBM_SOFT_RESET);
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H A D | sdma_v3_0.c | 1310 tmp = RREG32(mmSRBM_SOFT_RESET); in sdma_v3_0_soft_reset() 1313 WREG32(mmSRBM_SOFT_RESET, tmp); in sdma_v3_0_soft_reset() 1314 tmp = RREG32(mmSRBM_SOFT_RESET); in sdma_v3_0_soft_reset() 1319 WREG32(mmSRBM_SOFT_RESET, tmp); in sdma_v3_0_soft_reset() 1320 tmp = RREG32(mmSRBM_SOFT_RESET); in sdma_v3_0_soft_reset()
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H A D | uvd_v6_0.c | 1205 tmp = RREG32(mmSRBM_SOFT_RESET); in uvd_v6_0_soft_reset() 1208 WREG32(mmSRBM_SOFT_RESET, tmp); in uvd_v6_0_soft_reset() 1209 tmp = RREG32(mmSRBM_SOFT_RESET); in uvd_v6_0_soft_reset() 1214 WREG32(mmSRBM_SOFT_RESET, tmp); in uvd_v6_0_soft_reset() 1215 tmp = RREG32(mmSRBM_SOFT_RESET); in uvd_v6_0_soft_reset()
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H A D | gmc_v8_0.c | 1351 tmp = RREG32(mmSRBM_SOFT_RESET); in gmc_v8_0_soft_reset() 1354 WREG32(mmSRBM_SOFT_RESET, tmp); in gmc_v8_0_soft_reset() 1355 tmp = RREG32(mmSRBM_SOFT_RESET); in gmc_v8_0_soft_reset() 1360 WREG32(mmSRBM_SOFT_RESET, tmp); in gmc_v8_0_soft_reset() 1361 tmp = RREG32(mmSRBM_SOFT_RESET); in gmc_v8_0_soft_reset()
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H A D | uvd_v4_2.c | 295 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); in uvd_v4_2_start() 682 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, in uvd_v4_2_soft_reset()
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H A D | uvd_v3_1.c | 337 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); in uvd_v3_1_start() 782 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, in uvd_v3_1_soft_reset()
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H A D | uvd_v5_0.c | 348 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); in uvd_v5_0_start() 604 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, in uvd_v5_0_soft_reset()
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H A D | uvd_v7_0.c | 1529 tmp = RREG32(mmSRBM_SOFT_RESET); 1532 WREG32(mmSRBM_SOFT_RESET, tmp); 1533 tmp = RREG32(mmSRBM_SOFT_RESET); 1538 WREG32(mmSRBM_SOFT_RESET, tmp); 1539 tmp = RREG32(mmSRBM_SOFT_RESET);
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H A D | dce_v8_0.c | 2864 tmp = RREG32(mmSRBM_SOFT_RESET); in dce_v8_0_soft_reset() 2867 WREG32(mmSRBM_SOFT_RESET, tmp); in dce_v8_0_soft_reset() 2868 tmp = RREG32(mmSRBM_SOFT_RESET); in dce_v8_0_soft_reset() 2873 WREG32(mmSRBM_SOFT_RESET, tmp); in dce_v8_0_soft_reset() 2874 tmp = RREG32(mmSRBM_SOFT_RESET); in dce_v8_0_soft_reset()
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H A D | dce_v10_0.c | 2967 tmp = RREG32(mmSRBM_SOFT_RESET); in dce_v10_0_soft_reset() 2970 WREG32(mmSRBM_SOFT_RESET, tmp); in dce_v10_0_soft_reset() 2971 tmp = RREG32(mmSRBM_SOFT_RESET); in dce_v10_0_soft_reset() 2976 WREG32(mmSRBM_SOFT_RESET, tmp); in dce_v10_0_soft_reset() 2977 tmp = RREG32(mmSRBM_SOFT_RESET); in dce_v10_0_soft_reset()
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H A D | dce_v11_0.c | 3098 tmp = RREG32(mmSRBM_SOFT_RESET); in dce_v11_0_soft_reset() 3101 WREG32(mmSRBM_SOFT_RESET, tmp); in dce_v11_0_soft_reset() 3102 tmp = RREG32(mmSRBM_SOFT_RESET); in dce_v11_0_soft_reset() 3107 WREG32(mmSRBM_SOFT_RESET, tmp); in dce_v11_0_soft_reset() 3108 tmp = RREG32(mmSRBM_SOFT_RESET); in dce_v11_0_soft_reset()
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/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/oss/ |
H A D | oss_1_0_d.h | 262 #define mmSRBM_SOFT_RESET 0x0398 macro
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H A D | oss_2_4_d.h | 83 #define mmSRBM_SOFT_RESET 0x398 macro
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H A D | oss_3_0_1_d.h | 81 #define mmSRBM_SOFT_RESET 0x398 macro
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H A D | oss_3_0_d.h | 93 #define mmSRBM_SOFT_RESET 0x398 macro
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H A D | oss_2_0_d.h | 77 #define mmSRBM_SOFT_RESET 0x398 macro
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