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Searched refs:mmPHYPLLA_PIXCLK_RESYNC_CNTL (Results 1 – 10 of 10) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_offset.h28 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL … macro
H A Ddcn_3_0_3_offset.h117 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL … macro
H A Ddcn_3_0_1_offset.h200 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL … macro
H A Ddcn_1_0_offset.h464 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL … macro
H A Ddcn_2_1_0_offset.h152 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL … macro
H A Ddcn_3_0_2_offset.h132 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL … macro
H A Ddcn_2_0_0_offset.h132 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL … macro
H A Ddcn_3_0_0_offset.h114 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_11_2_d.h1069 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL 0x100 macro
H A Ddce_12_0_offset.h650 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL … macro