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Searched refs:mmMPCC1_MPCC_TOP_GAIN_BASE_IDX (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_offset.h3618 #define mmMPCC1_MPCC_TOP_GAIN_BASE_IDX … macro
H A Ddcn_3_0_3_offset.h6139 #define mmMPCC1_MPCC_TOP_GAIN_BASE_IDX … macro
H A Ddcn_3_0_1_offset.h10289 #define mmMPCC1_MPCC_TOP_GAIN_BASE_IDX … macro
H A Ddcn_2_1_0_offset.h5645 #define mmMPCC1_MPCC_TOP_GAIN_BASE_IDX … macro
H A Ddcn_3_0_2_offset.h12513 #define mmMPCC1_MPCC_TOP_GAIN_BASE_IDX … macro
H A Ddcn_2_0_0_offset.h6583 #define mmMPCC1_MPCC_TOP_GAIN_BASE_IDX … macro
H A Ddcn_3_0_0_offset.h13798 #define mmMPCC1_MPCC_TOP_GAIN_BASE_IDX … macro