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Searched refs:mmDSCL5_DSCL_2TAP_CONTROL_BASE_IDX (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_0_offset.h15545 #define mmDSCL5_DSCL_2TAP_CONTROL_BASE_IDX … macro
H A Ddcn_3_0_0_offset.h7398 #define mmDSCL5_DSCL_2TAP_CONTROL_BASE_IDX … macro