Searched refs:mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_0 (Results 1 – 2 of 2) sorted by relevance
51 #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_0 0x411E050 macro
5245 WREG32(mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_0 + (4 * i), in gaudi2_init_sm()10134 cq_base_l_addr = mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_0 + offset; in gaudi2_restore_user_sm_registers()10151 cq_base_l_addr = mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_0 + DCORE_OFFSET; in gaudi2_restore_user_sm_registers()