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Searched refs:mmCP_RB1_BASE_HI (Results 1 – 10 of 10) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_d.h199 #define mmCP_RB1_BASE_HI 0x30b2 macro
H A Dgfx_7_0_d.h199 #define mmCP_RB1_BASE_HI 0x30b2 macro
H A Dgfx_8_0_d.h223 #define mmCP_RB1_BASE_HI 0x30b2 macro
H A Dgfx_8_1_d.h224 #define mmCP_RB1_BASE_HI 0x30b2 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2589 #define mmCP_RB1_BASE_HI … macro
H A Dgc_9_2_1_offset.h2793 #define mmCP_RB1_BASE_HI … macro
H A Dgc_9_1_offset.h2859 #define mmCP_RB1_BASE_HI … macro
H A Dgc_10_1_0_offset.h4929 #define mmCP_RB1_BASE_HI … macro
H A Dgc_10_3_0_offset.h4590 #define mmCP_RB1_BASE_HI … macro
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v10_0.c6168 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); in gfx_v10_0_cp_gfx_resume()