Searched refs:mmCP_MEC1_F32_INT_DIS (Results 1 – 8 of 8) sorted by relevance
| /openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/ |
| H A D | gfx_8_0_d.h | 285 #define mmCP_MEC1_F32_INT_DIS 0x30bd macro
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| H A D | gfx_8_1_d.h | 286 #define mmCP_MEC1_F32_INT_DIS 0x30bd macro
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| /openbmc/linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfx_v9_0.c | 538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800),
603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800),
697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800),
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| /openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_0_offset.h | 2611 #define mmCP_MEC1_F32_INT_DIS … macro
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| H A D | gc_9_2_1_offset.h | 2815 #define mmCP_MEC1_F32_INT_DIS … macro
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| H A D | gc_9_1_offset.h | 2881 #define mmCP_MEC1_F32_INT_DIS … macro
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| H A D | gc_10_1_0_offset.h | 4945 #define mmCP_MEC1_F32_INT_DIS … macro
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| H A D | gc_10_3_0_offset.h | 4604 #define mmCP_MEC1_F32_INT_DIS … macro
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