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Searched refs:mmCP_HQD_GFX_CONTROL (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmes_v10_1.c371 WREG32_SOC15(GC, 0, mmCP_HQD_GFX_CONTROL, data); in mes_v10_1_init_aggregated_doorbell()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2805 #define mmCP_HQD_GFX_CONTROL … macro
H A Dgc_9_2_1_offset.h2989 #define mmCP_HQD_GFX_CONTROL … macro
H A Dgc_9_1_offset.h3033 #define mmCP_HQD_GFX_CONTROL … macro
H A Dgc_10_1_0_offset.h5057 #define mmCP_HQD_GFX_CONTROL … macro
H A Dgc_10_3_0_offset.h4716 #define mmCP_HQD_GFX_CONTROL … macro