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Searched refs:mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_offset.h264 #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX … macro
H A Ddcn_3_0_3_offset.h1232 #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX … macro
H A Ddcn_3_0_1_offset.h1433 #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX … macro
H A Ddcn_1_0_offset.h1873 #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX … macro
H A Ddcn_2_1_0_offset.h1479 #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX … macro
H A Ddcn_3_0_2_offset.h1405 #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX … macro
H A Ddcn_2_0_0_offset.h1517 #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX … macro
H A Ddcn_3_0_0_offset.h1419 #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_12_0_offset.h1547 #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX … macro