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Searched refs:misa_ext_mask (Results 1 – 6 of 6) sorted by relevance

/openbmc/qemu/target/riscv/kvm/
H A Dkvm-cpu.c197 bool value = env->misa_ext_mask & misa_bit; in kvm_cpu_get_misa_ext_cfg()
216 host_bit = env->misa_ext_mask & misa_bit; in kvm_cpu_set_misa_ext_cfg()
964 reg.addr = (uint64_t)&env->misa_ext_mask; in kvm_riscv_init_misa_ext_mask()
974 env->misa_ext = env->misa_ext_mask; in kvm_riscv_init_misa_ext_mask()
/openbmc/qemu/target/riscv/
H A Dmachine.c374 VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU),
H A Dcpu.h225 uint32_t misa_ext_mask; /* max ext for this cpu */ member
H A Dcpu.c328 env->misa_ext_mask = env->misa_ext = ext; in riscv_cpu_set_misa_ext()
H A Dcsr.c1685 val &= env->misa_ext_mask; in write_misa()
/openbmc/qemu/target/riscv/tcg/
H A Dtcg-cpu.c77 env->misa_ext_mask |= bit; in riscv_cpu_write_misa_bit()
80 env->misa_ext_mask &= ~bit; in riscv_cpu_write_misa_bit()