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Searched refs:misa_ext (Results 1 – 10 of 10) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dgdbstub.c117 if (env->misa_ext & RVD) { in riscv_gdb_get_fpu()
120 if (env->misa_ext & RVF) { in riscv_gdb_get_fpu()
332 if (env->misa_ext & RVD) { in riscv_cpu_register_gdb_regs_for_features()
336 } else if (env->misa_ext & RVF) { in riscv_cpu_register_gdb_regs_for_features()
H A Dcpu.h82 uint32_t misa_ext; member
224 uint32_t misa_ext; /* current extensions */ member
519 return (env->misa_ext & ext) != 0; in riscv_has_ext()
H A Dtranslate.c67 uint32_t misa_ext; member
123 return ctx->misa_ext & ext; in has_ext()
1222 ctx->misa_ext = env->misa_ext; in riscv_tr_init_disas_context()
H A Dcpu.c328 env->misa_ext_mask = env->misa_ext = ext; in riscv_cpu_set_misa_ext()
2213 .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVU,
2245 .misa_ext = RVS,
2817 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { in riscv_isa_string()
2835 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { in riscv_isa_extensions_list()
H A Dmachine.c372 VMSTATE_UINT32(env.misa_ext, RISCVCPU),
H A Dcsr.c1646 *val = int128_make128(env->misa_ext, (uint64_t)MXL_RV128 << 62); in read_misa_i128()
1668 *val = misa | env->misa_ext; in read_misa()
1676 uint32_t orig_misa_ext = env->misa_ext; in write_misa()
1702 if (val == env->misa_ext) { in write_misa()
1706 env->misa_ext = val; in write_misa()
1712 env->misa_ext, orig_misa_ext); in write_misa()
1714 env->misa_ext = orig_misa_ext; in write_misa()
1719 if (!(env->misa_ext & RVF)) { in write_misa()
/openbmc/qemu/target/riscv/tcg/
H A Dtcg-cpu.c76 env->misa_ext |= bit; in riscv_cpu_write_misa_bit()
79 env->misa_ext &= ~bit; in riscv_cpu_write_misa_bit()
689 if (!(profile->misa_ext & bit)) { in riscv_cpu_validate_profile()
782 env->misa_ext | rule->implied_misa_exts); in cpu_enable_implied_rule()
999 prev_val = env->misa_ext & misa_bit; in cpu_set_misa_ext_cfg()
1034 value = env->misa_ext & misa_bit; in cpu_get_misa_ext_cfg()
1141 if (!(profile->misa_ext & bit)) { in cpu_set_profile()
1341 riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV); in riscv_init_max_cpu_extensions()
/openbmc/qemu/linux-user/riscv/
H A Dcpu_loop.c107 if ((env->misa_ext & RVE) && !(env->elf_flags & EF_RISCV_RVE)) { in target_cpu_copy_regs()
/openbmc/qemu/target/riscv/kvm/
H A Dkvm-cpu.c266 env->misa_ext &= ~misa_bit; in kvm_riscv_update_cpu_misa_ext()
974 env->misa_ext = env->misa_ext_mask; in kvm_riscv_init_misa_ext_mask()
/openbmc/qemu/linux-user/
H A Delfload.c1865 return cpu->env.misa_ext & mask; in get_elf_hwcap()