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Searched refs:mhpmeventh_val (Results 1 – 4 of 4) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dpmu.c113 (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_MINH)) || in riscv_pmu_incr_ctr_rv32()
115 (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_VSINH)) || in riscv_pmu_incr_ctr_rv32()
117 (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_VUINH)) || in riscv_pmu_incr_ctr_rv32()
119 (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_SINH)) || in riscv_pmu_incr_ctr_rv32()
121 (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_UINH))) { in riscv_pmu_incr_ctr_rv32()
131 if (!(env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_OF)) { in riscv_pmu_incr_ctr_rv32()
132 env->mhpmeventh_val[ctr_idx] |= MHPMEVENTH_BIT_OF; in riscv_pmu_incr_ctr_rv32()
429 mhpmevent_val = env->mhpmeventh_val[ctr_idx]; in pmu_hpmevent_is_of_set()
445 mhpmevent_val = &env->mhpmeventh_val[ctr_idx]; in pmu_hpmevent_set_of_if_clear()
H A Dmachine.c405 VMSTATE_UINTTL_ARRAY(env.mhpmeventh_val, RISCVCPU, RV_MAX_MHPMEVENTS),
H A Dcpu.h386 target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; member
H A Dcsr.c955 ((uint64_t)env->mhpmeventh_val[evt_index] << 32); in write_mhpmevent()
978 *val = env->mhpmeventh_val[evt_index]; in read_mhpmeventh()
1001 env->mhpmeventh_val[evt_index] = mhpmevth_val; in write_mhpmeventh()
1027 ((uint64_t)env->mhpmeventh_val[counter_idx] << 32) : in riscv_pmu_ctr_get_fixed_counters_val()
1203 mhpm_evt_val = env->mhpmeventh_val; in read_scountovf()