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Searched refs:ecc_ctrl (Results 1 – 9 of 9) sorted by relevance

/openbmc/u-boot/cmd/ti/
H A Dddr3.c189 u32 ecc_ctrl = readl(&emif->emif_ecc_ctrl_reg); in ddr_memory_ecc_err() local
210 ecc_ctrl = ECC_START_ADDR1 | (ECC_END_ADDR1 << 16); in ddr_memory_ecc_err()
214 writel(ecc_ctrl, &emif->emif_ecc_ctrl_reg); in ddr_memory_ecc_err()
231 u32 start_addr, end_addr, range, ecc_ctrl; in is_addr_valid() local
234 ecc_ctrl = EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK; in is_addr_valid()
237 ecc_ctrl = readl(&emif->emif_ecc_ctrl_reg); in is_addr_valid()
242 if (ecc_ctrl & EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK) { in is_addr_valid()
253 if (ecc_ctrl & EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK) { in is_addr_valid()
270 u32 ecc_ctrl = readl(&emif->emif_ecc_ctrl_reg); in is_ecc_enabled() local
272 return (ecc_ctrl & EMIF_ECC_CTRL_REG_ECC_EN_MASK) && in is_ecc_enabled()
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/openbmc/u-boot/arch/arm/mach-keystone/
H A Dinit.c40 u32 ecc_ctrl[KS2_OSR_NUM_RAM_BANKS]; in osr_init() local
62 ecc_ctrl[i] = readl(base + KS2_OSR_ECC_CTRL) ^ in osr_init()
65 writel(ecc_ctrl[i], KS2_MSMC_DATA_BASE + i * 4); in osr_init()
66 writel(ecc_ctrl[i], base + KS2_OSR_ECC_CTRL); in osr_init()
75 writel(ecc_ctrl[i] | in osr_init()
/openbmc/linux/drivers/mtd/nand/raw/
H A Drenesas-nand-controller.c205 u32 ecc_ctrl; member
312 writel_relaxed(rnand->ecc_ctrl, rnandc->regs + ECC_CTRL_REG); in rnandc_select_target()
1036 rnand->ecc_ctrl |= ECC_CTRL_CAP_2B; in rnandc_hw_ecc_controller_init()
1040 rnand->ecc_ctrl |= ECC_CTRL_CAP_4B; in rnandc_hw_ecc_controller_init()
1044 rnand->ecc_ctrl |= ECC_CTRL_CAP_8B; in rnandc_hw_ecc_controller_init()
1048 rnand->ecc_ctrl |= ECC_CTRL_CAP_16B; in rnandc_hw_ecc_controller_init()
1052 rnand->ecc_ctrl |= ECC_CTRL_CAP_24B; in rnandc_hw_ecc_controller_init()
1056 rnand->ecc_ctrl |= ECC_CTRL_CAP_32B; in rnandc_hw_ecc_controller_init()
1063 rnand->ecc_ctrl |= ECC_CTRL_ERR_THRESHOLD(chip->ecc.strength); in rnandc_hw_ecc_controller_init()
/openbmc/u-boot/drivers/mtd/nand/raw/
H A Dlpc32xx_nand_slc.c171 u32 i, dmasrc, ctrl, ecc_ctrl, oob_ctrl, dmadst; in lpc32xx_nand_dma_configure() local
179 ecc_ctrl = 0x5 | in lpc32xx_nand_dma_configure()
254 dmalist_cur_ecc->next_ctrl = ecc_ctrl; in lpc32xx_nand_dma_configure()
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dumc_v6_7.c495 uint32_t ecc_ctrl_addr, ecc_ctrl; in umc_v6_7_query_ras_poison_mode_per_channel() local
499 ecc_ctrl = RREG32_PCIE((ecc_ctrl_addr + in umc_v6_7_query_ras_poison_mode_per_channel()
502 return REG_GET_FIELD(ecc_ctrl, UMCCH0_0_EccCtrl, UCFatalEn); in umc_v6_7_query_ras_poison_mode_per_channel()
/openbmc/linux/drivers/edac/
H A Damd64_edac.h311 u32 ecc_ctrl; /* DRAM ECC Control reg */ member
H A Dpnd2_edac.c415 static struct d_cr_ecc_ctrl ecc_ctrl[DNV_NUM_CHANNELS]; variable
471 if (RD_REGP(&ecc_ctrl[i], d_cr_ecc_ctrl, dnv_dports[i]) || in dnv_get_registers()
1079 if (DIMMS_PRESENT(d) && !ecc_ctrl[ch].eccen) { in check_unit()
H A Damd64_edac.c1619 edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl); in umc_dump_misc_regs()
3184 amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &umc->ecc_ctrl); in umc_read_mc_regs()
3817 edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl); in gpu_dump_misc_regs()
3920 amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &umc->ecc_ctrl); in gpu_read_mc_regs()
/openbmc/u-boot/arch/x86/cpu/quark/
H A Dsmc.c2547 u32 ecc_ctrl; in ecc_enable() local
2567 ecc_ctrl = (DECCCTRL_SBEEN | DECCCTRL_DBEEN | DECCCTRL_ENCBGEN); in ecc_enable()
2568 msg_port_write(MEM_CTLR, DECCCTRL, ecc_ctrl); in ecc_enable()