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Searched refs:div_val (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/drivers/clk/mmp/
H A Dclk-mix.c131 static int _set_rate(struct mmp_clk_mix *mix, u32 mux_val, u32 div_val, in _set_rate() argument
156 mux_div |= MMP_CLK_BITS_SET_VAL(div_val, width, shift); in _set_rate()
277 u32 div_val, mux_val; in mmp_clk_mix_set_rate_and_parent() local
280 div_val = _get_div_val(mix, div); in mmp_clk_mix_set_rate_and_parent()
283 return _set_rate(mix, mux_val, div_val, 1, 1); in mmp_clk_mix_set_rate_and_parent()
350 u32 div_val, mux_val; in mmp_clk_set_parent() local
361 div_val = _get_div_val(mix, item->divisor); in mmp_clk_set_parent()
367 div_val = 0; in mmp_clk_set_parent()
370 return _set_rate(mix, mux_val, div_val, 1, div_val ? 1 : 0); in mmp_clk_set_parent()
/openbmc/linux/drivers/clk/
H A Dclk-loongson1.c111 int val, div_val; in ls1x_divider_set_rate() local
114 div_val = divider_get_val(rate, parent_rate, d->table, in ls1x_divider_set_rate()
116 if (div_val < 0) in ls1x_divider_set_rate()
117 return div_val; in ls1x_divider_set_rate()
131 val |= (u32)div_val << d->shift; in ls1x_divider_set_rate()
H A Dclk-k210.c754 u32 reg, div_val; in k210_clk_get_rate() local
760 div_val = (reg >> cfg->div_shift) & GENMASK(cfg->div_width - 1, 0); in k210_clk_get_rate()
764 return parent_rate / (div_val + 1); in k210_clk_get_rate()
766 return parent_rate / ((div_val + 1) * 2); in k210_clk_get_rate()
768 return parent_rate / (2UL << div_val); in k210_clk_get_rate()
/openbmc/linux/drivers/clk/x86/
H A Dclk-cgu.h187 unsigned int div_val; member
237 .div_val = _v, \
275 .div_val = _v, \
295 .div_val = _v, \
H A Dclk-cgu.c31 list->div_width, list->div_val); in lgm_clk_register_fixed()
233 lgm_set_clk_val(div->membase, reg, shift, width, list->div_val); in lgm_clk_register_divider()
252 list->div_width, list->div_val); in lgm_clk_register_fixed_factor()
/openbmc/linux/drivers/media/cec/platform/s5p/
H A Dexynos_hdmi_cecctrl.c25 u32 div_ratio, div_val; in s5p_cec_set_divider() local
42 div_val = CEC_DIV_RATIO * 0.00005 - 1; in s5p_cec_set_divider()
47 writeb(div_val, cec->reg + S5P_CEC_DIVISOR_0); in s5p_cec_set_divider()
/openbmc/linux/drivers/clk/imx/
H A Dclk-pll14xx.c288 u32 tmp, div_val; in clk_pll1416x_set_rate() local
321 div_val = FIELD_PREP(MDIV_MASK, rate->mdiv) | FIELD_PREP(PDIV_MASK, rate->pdiv) | in clk_pll1416x_set_rate()
323 writel_relaxed(div_val, pll->base + DIV_CTL0); in clk_pll1416x_set_rate()