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Searched refs:ddr_phy_regs (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/mips/mach-jz47xx/jz4780/
H A Dsdram.c74 writel(ddr_config->mr0, ddr_phy_regs + DDRP_MR0); in ddr_phy_init()
75 writel(ddr_config->mr1, ddr_phy_regs + DDRP_MR1); in ddr_phy_init()
76 writel(0, ddr_phy_regs + DDRP_ODTCR); in ddr_phy_init()
77 writel(0, ddr_phy_regs + DDRP_MR2); in ddr_phy_init()
79 writel(ddr_config->ptr0, ddr_phy_regs + DDRP_PTR0); in ddr_phy_init()
91 ddr_phy_regs + DDRP_PGCR); in ddr_phy_init()
99 reg = readl(ddr_phy_regs + DDRP_PGSR); in ddr_phy_init()
114 ddr_phy_regs + DDRP_PIR); in ddr_phy_init()
119 reg = readl(ddr_phy_regs + DDRP_PGSR); in ddr_phy_init()
131 reg = readl(ddr_phy_regs + DDRP_PGSR); in ddr_phy_init()
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/openbmc/u-boot/arch/arm/mach-imx/mx7/
H A Dddr.c34 struct ddr_phy *const ddr_phy_regs = in mx7_dram_cfg() local
78 writel(ddr_phy_regs_val->phy_con0, &ddr_phy_regs->phy_con0); in mx7_dram_cfg()
79 writel(ddr_phy_regs_val->phy_con1, &ddr_phy_regs->phy_con1); in mx7_dram_cfg()
80 writel(ddr_phy_regs_val->phy_con4, &ddr_phy_regs->phy_con4); in mx7_dram_cfg()
81 writel(ddr_phy_regs_val->mdll_con0, &ddr_phy_regs->mdll_con0); in mx7_dram_cfg()
82 writel(ddr_phy_regs_val->drvds_con0, &ddr_phy_regs->drvds_con0); in mx7_dram_cfg()
83 writel(ddr_phy_regs_val->offset_wr_con0, &ddr_phy_regs->offset_wr_con0); in mx7_dram_cfg()
84 writel(ddr_phy_regs_val->offset_rd_con0, &ddr_phy_regs->offset_rd_con0); in mx7_dram_cfg()
87 &ddr_phy_regs->cmd_sdll_con0); in mx7_dram_cfg()
90 &ddr_phy_regs->cmd_sdll_con0); in mx7_dram_cfg()
[all …]