Searched refs:cur_stage (Results 1 – 4 of 4) sorted by relevance
31 u8 cur_stage; in boot_progress_show() local41 cur_stage = reg & 0xff; in boot_progress_show()49 if (boot_stage > cur_stage) in boot_progress_show()59 if (boot_stage < cur_stage) { in boot_progress_show()
141 u32 cur_stage; member
94 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16); in reg_file_set_group()99 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff); in reg_file_set_stage()105 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8); in reg_file_set_sub_stage()3607 writel(0, &sdr_reg_file->cur_stage); in initialize_reg_file()
2421 u8 cur_stage = 0; in rtl8821ae_dm_refresh_basic_rate_mask() local2425 cur_stage = 0; in rtl8821ae_dm_refresh_basic_rate_mask()2427 cur_stage = 1; in rtl8821ae_dm_refresh_basic_rate_mask()2429 cur_stage = 3; in rtl8821ae_dm_refresh_basic_rate_mask()2431 cur_stage = 2; in rtl8821ae_dm_refresh_basic_rate_mask()2433 if (cur_stage != stage) { in rtl8821ae_dm_refresh_basic_rate_mask()2434 if (cur_stage == 1) { in rtl8821ae_dm_refresh_basic_rate_mask()2438 } else if (cur_stage == 3 && (stage == 1 || stage == 2)) { in rtl8821ae_dm_refresh_basic_rate_mask()2443 stage = cur_stage; in rtl8821ae_dm_refresh_basic_rate_mask()