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Searched refs:cm_clkmode_dpll_core (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/arch/arm/mach-omap2/omap5/
H A Dprcm-regs.c20 .cm_clkmode_dpll_core = 0x4a004120,
476 .cm_clkmode_dpll_core = 0x4a004120,
771 .cm_clkmode_dpll_core = 0x4a005120,
/openbmc/u-boot/arch/arm/mach-omap2/omap4/
H A Dprcm-regs.c19 .cm_clkmode_dpll_core = 0x4a004120,
/openbmc/u-boot/arch/arm/mach-omap2/
H A Dclocks-common.c390 do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params, in setup_dplls()
393 do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params, in setup_dplls()
H A Demif-common.c1524 bypass_dpll((*prcm)->cm_clkmode_dpll_core); in sdram_init()
/openbmc/u-boot/arch/arm/include/asm/
H A Domap_common.h22 u32 cm_clkmode_dpll_core; member