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Searched refs:cl_value (Results 1 – 1 of 1) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training.c344 u32 cl_value = 0, cwl_val = 0; in hws_ddr3_tip_init_controller() local
510 cl_value = in hws_ddr3_tip_init_controller()
518 cl_value, cwl_val)); in hws_ddr3_tip_init_controller()
565 cl_value, cwl_val); in hws_ddr3_tip_init_controller()
1256 cl_value = in ddr3_tip_freq_set()
1263 if (cl_value == 0) { in ddr3_tip_freq_set()
1539 ((cl_value - cwl_value + 6) << 8) | in ddr3_tip_freq_set()
1540 ((cl_value - 1) << 12) | ((cl_value + 6) << 16); in ddr3_tip_freq_set()
1590 u32 val = (cl_value - cwl_value + 6); in ddr3_tip_write_odt()
1593 (((cl_value - 1) & 0xf) << 12) | in ddr3_tip_write_odt()
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