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Searched refs:cfgBIFPLR5_PCIE_LANE_0_EQUALIZATION_CNTL (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_7_0_offset.h3176 #define cfgBIFPLR5_PCIE_LANE_0_EQUALIZATION_CNTL … macro
H A Dnbio_7_2_0_offset.h3563 #define cfgBIFPLR5_PCIE_LANE_0_EQUALIZATION_CNTL … macro