Searched refs:XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLK_SEL_MASK (Results 1 – 1 of 1) sorted by relevance
196 #define XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLK_SEL_MASK (0xf << 4) macro247 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLK_SEL_MASK; in pcie_phy_enable()