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Searched refs:VEXT_VER_1_00_0_STR (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dcpu.h110 #define VEXT_VER_1_00_0_STR "v1.0" macro
H A Dcpu.c1870 if (g_strcmp0(value, VEXT_VER_1_00_0_STR) != 0) { in prop_vext_spec_set()
1882 const char *value = VEXT_VER_1_00_0_STR; in prop_vext_spec_get()