Home
last modified time | relevance | path

Searched refs:TTBCR_IRGN0_WT (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/arch/arm/lib/
H A Dcache-cp15.c133 reg |= TTBCR_ORGN0_WT | TTBCR_IRGN0_WT; in mmu_setup()
/openbmc/u-boot/arch/arm/cpu/armv7/ls102xa/
H A Dcpu.c54 #define TTBCR_IRGN0_WT (2 << 8) macro
/openbmc/u-boot/arch/arm/include/asm/
H A Dsystem.h429 #define TTBCR_IRGN0_WT (2 << 8) macro