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Searched refs:TM_WORD2 (Results 1 – 10 of 10) sorted by relevance

/openbmc/qemu/tests/qtest/
H A Dpnv-xive2-test.c116 set_tima32(qts, i, TM_QW2_HV_POOL + TM_WORD2, TM_QW2W2_VP | nvp_idx); in reset_pool_threads()
139 set_tima32(qts, i, TM_QW3_HV_PHYS + TM_WORD2, 0x80000000); in reset_hw_threads()
290 qw1w2 = get_tima32(qts, target_pir, TM_QW1_OS + TM_WORD2); in test_pull_thread_ctx_to_odd_thread_cl()
291 qw2w2 = get_tima32(qts, target_pir, TM_QW2_HV_POOL + TM_WORD2); in test_pull_thread_ctx_to_odd_thread_cl()
292 qw3b8 = get_tima8(qts, target_pir, TM_QW3_HV_PHYS + TM_WORD2); in test_pull_thread_ctx_to_odd_thread_cl()
303 memcpy(&cl_word, &cl_pair[XIVE_ODD_CL + TM_QW1_OS + TM_WORD2], 4); in test_pull_thread_ctx_to_odd_thread_cl()
305 memcpy(&cl_word, &cl_pair[XIVE_ODD_CL + TM_QW2_HV_POOL + TM_WORD2], 4); in test_pull_thread_ctx_to_odd_thread_cl()
308 cl_pair[XIVE_ODD_CL + TM_QW3_HV_PHYS + TM_WORD2]); in test_pull_thread_ctx_to_odd_thread_cl()
311 word2 = get_tima32(qts, target_pir, TM_QW1_OS + TM_WORD2); in test_pull_thread_ctx_to_odd_thread_cl()
313 word2 = get_tima32(qts, target_pir, TM_QW2_HV_POOL + TM_WORD2); in test_pull_thread_ctx_to_odd_thread_cl()
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/openbmc/qemu/hw/intc/
H A Dxive2.c378 memcpy(&tctx->regs[cur_ring + TM_WORD2], &ringw2_new, 4); in xive2_tm_pull_ctx()
422 data[0x7] = regs[TM_QW3_HV_PHYS + TM_WORD2] & 0x80; in xive2_tm_report_line_gen1()
423 data[0x7] |= (regs[TM_QW2_HV_POOL + TM_WORD2] & 0x80) >> 1; in xive2_tm_report_line_gen1()
424 data[0x7] |= (regs[TM_QW1_OS + TM_WORD2] & 0x80) >> 2; in xive2_tm_report_line_gen1()
425 data[0x7] |= (regs[TM_QW3_HV_PHYS + TM_WORD2] & 0x3); in xive2_tm_report_line_gen1()
430 if (regs[TM_QW0_USER + TM_WORD2] & 0x80) { in xive2_tm_report_line_gen1()
435 data[0xC] = regs[TM_QW0_USER + TM_WORD2]; in xive2_tm_report_line_gen1()
438 data[0xD] = regs[TM_QW0_USER + TM_WORD2 + 1]; in xive2_tm_report_line_gen1()
439 data[0xE] = regs[TM_QW0_USER + TM_WORD2 + 2]; in xive2_tm_report_line_gen1()
440 data[0xF] = regs[TM_QW0_USER + TM_WORD2 + 3]; in xive2_tm_report_line_gen1()
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H A Dxive.c170 if (pool_regs[TM_WORD2] & 0x80) { in xive_tctx_set_cppr()
223 memcpy(&tctx->regs[TM_QW2_HV_POOL + TM_WORD2], &qw2w2, 4); in xive_tm_pull_pool_ctx()
230 uint8_t qw3b8_prev = tctx->regs[TM_QW3_HV_PHYS + TM_WORD2]; in xive_tm_pull_phys_ctx()
234 tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] = qw3b8; in xive_tm_pull_phys_ctx()
241 tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] = value & 0xff; in xive_tm_vt_push()
247 return tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] & 0xff; in xive_tm_vt_poll()
449 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); in xive_tctx_set_os_cam()
562 { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive_tm_push_os_ctx,
566 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push,
568 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL,
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H A Dspapr_xive.c658 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); in xive_tctx_set_os_cam()
/openbmc/linux/arch/powerpc/include/asm/
H A Dxive-regs.h79 #define TM_WORD2 0x8 macro
/openbmc/linux/arch/powerpc/sysdev/xive/
H A Dnative.c402 if (in_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2) & TM_QW2W2_VP) in xive_native_setup_cpu()
428 out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2, TM_QW2W2_VP | vp_cam); in xive_native_setup_cpu()
H A Dspapr.c652 in_be32(xive_tima + TM_QW1_OS + TM_WORD2)); in xive_spapr_setup_cpu()
/openbmc/qemu/include/hw/ppc/
H A Dxive_regs.h93 #define TM_WORD2 0x8 macro
H A Dxive.h367 return *((uint32_t *) &ring[TM_WORD2]); in xive_tctx_word2()
/openbmc/linux/arch/powerpc/kvm/
H A Dbook3s_xive.c702 __raw_writel(vcpu->arch.xive_cam_word, tima + TM_QW1_OS + TM_WORD2); in kvmppc_xive_push_vcpu()