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Searched refs:TM_CPPR (Results 1 – 4 of 4) sorted by relevance

/openbmc/qemu/tests/qtest/
H A Dpnv-xive2-test.c262 set_tima8(qts, target_pir, TM_QW3_HV_PHYS + TM_CPPR, 0xFF); in test_hw_irq()
335 set_tima8(qts, target_pir, TM_QW3_HV_PHYS + TM_CPPR, 0xFF); in test_pool_irq()
453 set_tima8(qts, chosen_one, TM_QW3_HV_PHYS + TM_CPPR, 0xFF); in test_hw_group_irq()
484 set_tima8(qts, i, TM_QW3_HV_PHYS + TM_CPPR, blocking_priority); in test_hw_group_irq_backlog()
511 set_tima8(qts, chosen_one, TM_QW3_HV_PHYS + TM_CPPR, priority + 1); in test_hw_group_irq_backlog()
537 set_tima8(qts, chosen_one, TM_QW3_HV_PHYS + TM_CPPR, 0xFF); in test_hw_group_irq_backlog()
/openbmc/qemu/hw/intc/
H A Dxive.c109 g_assert(tctx->regs[TM_QW2_HV_POOL + TM_CPPR] == 0); in xive_tctx_accept()
119 sig_regs[TM_CPPR] = cppr; in xive_tctx_accept()
135 sig_regs[TM_CPPR], sig_regs[TM_NSR]); in xive_tctx_accept()
138 return ((uint64_t)nsr << 8) | sig_regs[TM_CPPR]; in xive_tctx_accept()
152 if (pipr < sig_regs[TM_CPPR]) { in xive_tctx_pipr_set()
168 sig_regs[TM_CPPR], sig_regs[TM_NSR]); in xive_tctx_pipr_set()
196 g_assert(tctx->regs[TM_QW2_HV_POOL + TM_CPPR] == 0); in xive_tctx_set_cppr()
207 sig_regs[TM_CPPR] = cppr; in xive_tctx_set_cppr()
699 { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, true, true,
703 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, true, true,
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/openbmc/qemu/include/hw/ppc/
H A Dxive_regs.h74 #define TM_CPPR 0x1 /* - + - + */ macro
H A Dxive.h570 g_assert(tctx->regs[TM_QW2_HV_POOL + TM_CPPR] == 0); in xive_tctx_signal_regs()