Searched refs:TEGRA_CEC_INT_STAT_TX_REGISTER_UNDERRUN (Results 1 – 2 of 2) sorted by relevance
83 #define TEGRA_CEC_INT_STAT_TX_REGISTER_UNDERRUN BIT(1) macro
107 if (status & TEGRA_CEC_INT_STAT_TX_REGISTER_UNDERRUN) { in tegra_cec_irq_handler()