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Searched refs:TEGRA20_CLK_PLL_A_OUT0 (Results 1 – 19 of 19) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dtegra20-car.h136 #define TEGRA20_CLK_PLL_A_OUT0 113 macro
/openbmc/u-boot/include/dt-bindings/clock/
H A Dtegra20-car.h135 #define TEGRA20_CLK_PLL_A_OUT0 113 macro
/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra20-plutux.dts58 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
H A Dtegra20-tec.dts67 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
H A Dtegra20-medcom-wide.dts93 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
H A Dtegra20-trimslice.dts473 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
H A Dtegra20-ventana.dts720 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
H A Dtegra20-paz00.dts687 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
H A Dtegra20-harmony.dts759 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
H A Dtegra20-colibri.dtsi774 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
H A Dtegra20-seaboard.dts918 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
H A Dtegra20.dtsi404 assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_A_OUT0>;
H A Dtegra20-asus-tf101.dts1203 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
H A Dtegra20-acer-a500-picasso.dts1435 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
/openbmc/linux/drivers/clk/tegra/
H A Dclk-tegra20.c434 { .con_id = "pll_a_out0", .dt_id = TEGRA20_CLK_PLL_A_OUT0 },
689 clks[TEGRA20_CLK_PLL_A_OUT0] = clk; in tegra20_pll_init()
1031 { TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 0 },
1032 { TEGRA20_CLK_I2S1, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
1033 { TEGRA20_CLK_I2S2, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
/openbmc/u-boot/arch/arm/dts/
H A Dtegra20-paz00.dts632 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
H A Dtegra20-ventana.dts725 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
H A Dtegra20-harmony.dts810 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
H A Dtegra20-seaboard.dts980 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,