Searched refs:TEGRA194_CLK_PLLA_OUT0 (Results 1 – 2 of 2) sorted by relevance
110 #define TEGRA194_CLK_PLLA_OUT0 104 macro
250 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;264 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;278 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;292 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;306 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;320 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;425 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;438 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;3119 <&bpmp TEGRA194_CLK_PLLA_OUT0>;3122 <&bpmp TEGRA194_CLK_PLLA_OUT0>,[all …]