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Searched refs:TCC_REDUNDANCY__MC_SEL0_MASK (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h13615 #define TCC_REDUNDANCY__MC_SEL0_MASK 0x1 macro
H A Dgfx_8_0_sh_mask.h15551 #define TCC_REDUNDANCY__MC_SEL0_MASK 0x1 macro
H A Dgfx_8_1_sh_mask.h16121 #define TCC_REDUNDANCY__MC_SEL0_MASK 0x1 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h9169 #define TCC_REDUNDANCY__MC_SEL0_MASK … macro
H A Dgc_9_2_1_sh_mask.h10456 #define TCC_REDUNDANCY__MC_SEL0_MASK … macro
H A Dgc_9_1_sh_mask.h10670 #define TCC_REDUNDANCY__MC_SEL0_MASK … macro
H A Dgc_9_4_2_sh_mask.h27936 #define TCC_REDUNDANCY__MC_SEL0_MASK … macro