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Searched refs:S_STAGE (Results 1 – 1 of 1) sorted by relevance

/openbmc/qemu/hw/riscv/
H A Driscv-iommu.c270 S_STAGE = 0, in riscv_iommu_spa_fetch() enumerator
381 pass = en_g ? G_STAGE : S_STAGE; in riscv_iommu_spa_fetch()
445 pass = S_STAGE; in riscv_iommu_spa_fetch()
455 if (pass == S_STAGE && (iotlb->perm & IOMMU_WO) && in riscv_iommu_spa_fetch()