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Searched refs:SPR_TIR (Results 1 – 6 of 6) sorted by relevance

/openbmc/qemu/target/ppc/
H A Dmisc_helper.c76 ts_mask = ~(1U << (8 + env->spr[SPR_TIR])); in helper_spr_write_CTRL()
77 ts = run << (8 + env->spr[SPR_TIR]); in helper_spr_write_CTRL()
H A Dcpu.h1884 #define SPR_TIR (0x1BE) macro
H A Dcpu_init.c2999 spr_register(env, SPR_TIR, "TIR", in init_proc_e500()
5507 spr_register(env, SPR_TIR, "TIR", in register_rmor_sprs()
/openbmc/qemu/hw/ppc/
H A Dspapr_cpu_core.c274 env->spr_cb[SPR_TIR].default_value = thread_index; in spapr_realize_vcpu()
H A Dpnv_core.c304 ppc_spr_t *tir_spr = &env->spr_cb[SPR_TIR]; in pnv_core_cpu_realize()
H A Dppc.c1525 return env->spr_cb[SPR_TIR].default_value; in ppc_cpu_tir()