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Searched refs:SIFIVE_U_DEV_UART1 (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/include/hw/riscv/
H A Dsifive_u.h88 SIFIVE_U_DEV_UART1, enumerator
/openbmc/qemu/hw/riscv/
H A Dsifive_u.c79 [SIFIVE_U_DEV_UART1] = { 0x10011000, 0x1000 },
471 (long)memmap[SIFIVE_U_DEV_UART1].base); in create_fdt()
475 0x0, memmap[SIFIVE_U_DEV_UART1].base, in create_fdt()
476 0x0, memmap[SIFIVE_U_DEV_UART1].size); in create_fdt()
844 sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base, in sifive_u_soc_realize()