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Searched refs:SIFIVE_U_DEV_PWM0 (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/include/hw/riscv/
H A Dsifive_u.h98 SIFIVE_U_DEV_PWM0, enumerator
/openbmc/qemu/hw/riscv/
H A Dsifive_u.c80 [SIFIVE_U_DEV_PWM0] = { 0x10020000, 0x1000 },
439 (long)memmap[SIFIVE_U_DEV_PWM0].base); in create_fdt()
443 0x0, memmap[SIFIVE_U_DEV_PWM0].base, in create_fdt()
444 0x0, memmap[SIFIVE_U_DEV_PWM0].size); in create_fdt()
908 memmap[SIFIVE_U_DEV_PWM0].base + (0x1000 * i)); in sifive_u_soc_realize()