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Searched refs:SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-uniphier/clk/
H A Dpll-pro4.c25 clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) in vpll_init()
55 clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) { in vpll_init()
/openbmc/u-boot/arch/arm/mach-uniphier/
H A Dsg-regs.h83 #define SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ (0x3 << 16) macro