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/openbmc/linux/Documentation/networking/device_drivers/ethernet/freescale/
H A Ddpaa.rst44 -Ports / Tx Rx \ ... / Tx Rx \
62 |Rx | |Rx | |Tx | |Tx | | driver |
83 Rx Dfl FQ default reception FQ
84 Rx Err FQ Rx error frames FQ
155 The driver has Rx and Tx checksum offloading for UDP and TCP. Currently the Rx
184 Traffic coming on the DPAA Rx queues or on the DPAA Tx confirmation
194 received on the default Rx frame queue. The default DPAA Rx frame
204 128 Rx frame queues that are configured to dedicated channels, in a
249 - Rx packets count per CPU
254 - Rx error count per CPU
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/can/
H A Dbosch,m_can.yaml57 and each element(e.g Rx FIFO or Tx Buffer and etc) number
72 Rx FIFO 0 0-64 elements / 0-1152 words
73 Rx FIFO 1 0-64 elements / 0-1152 words
74 Rx Buffers 0-64 elements / 0-1152 words
92 - description: Rx FIFO 0 0-64 elements / 0-1152 words
95 - description: Rx FIFO 1 0-64 elements / 0-1152 words
98 - description: Rx Buffers 0-64 elements / 0-1152 words
/openbmc/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dfsl,cpm1-tsa.yaml59 The hardware can use four dedicated pins for Tx clock, Tx sync, Rx
60 clock and Rx sync or use only two pins, Tx/Rx clock and Tx/Rx sync.
85 Indicates the delay between the Rx sync and the first bit of the Rx
119 A list of tuple that indicates the Tx or Rx time-slots routes.
127 The source (Tx) or destination (Rx) serial interface
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dnvidia,tegra210-admaif.yaml14 ADMAIF Rx channel.
66 DMA channel specifiers, equally divided for Tx and Rx.
73 Should be "rx1", "rx2" ... "rx10" for DMA Rx channel
82 DMA channel specifiers, equally divided for Tx and Rx.
89 Should be "rx1", "rx2" ... "rx20" for DMA Rx channel
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,gcc-sm8350.yaml28 - description: UFS card Rx symbol 0 clock source (Optional clock)
29 - description: UFS card Rx symbol 1 clock source (Optional clock)
31 - description: UFS phy Rx symbol 0 clock source (Optional clock)
32 - description: UFS phy Rx symbol 1 clock source (Optional clock)
H A Dqcom,sm8550-gcc.yaml29 - description: UFS Phy Rx symbol 0 clock source
30 - description: UFS Phy Rx symbol 1 clock source
H A Dqcom,gcc-sm8450.yaml29 - description: UFS Phy Rx symbol 0 clock source (Optional clock)
30 - description: UFS Phy Rx symbol 1 clock source (Optional clock)
/openbmc/linux/Documentation/networking/device_drivers/ethernet/amazon/
H A Dena.rst25 processing by providing multiple Tx/Rx queue pairs (the maximum number
27 interrupt vector per Tx/Rx queue pair, adaptive interrupt moderation,
50 ena_eth_com.[ch] Tx/Rx data path.
124 I/O operations are based on Tx and Rx Submission Queues (Tx SQ and Rx
149 The Rx SQs support only the regular mode.
151 The driver supports multi-queue for both Tx and Rx. This has various
182 <interface name>-Tx-Rx-<queue index>
246 - The ENA device supports RSS that allows flexible Rx traffic
297 Rx section in DATA PATH
313 and is reused for future Rx packets.
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/openbmc/libmctp/docs/bindings/
H A Dvendor-ibm-astlpc.md244 For all defined versions, only a single MCTP packet is present in the Rx and Tx
250 transmission unit. The Rx and Tx buffers must be sized to accommodate packets up
272 For all protocol versions, the following properties must be upheld for the Rx
306 | 0x02 | Rx Complete |
359 - Only the BMC may write to the Rx buffer described in the control area
367 3. The Rx side now owns the buffer, and reads the message from its Rx area
368 4. The Rx side sends a `Rx Complete` once done, indicating that the buffer
413 | 2 | ✓ | ✓ | ✓ | The host waits on any previous `Rx Complete` message …
414 … | The host writes the packet data and medium-specific metadata to its Tx area (BMC Rx area) |
418 | 7 | ✓ | ✓ | ✓ | The BMC sends the `Rx Complete` command, transferring ownership of its R…
[all …]
/openbmc/linux/drivers/media/platform/xilinx/
H A DKconfig18 tristate "Xilinx CSI-2 Rx Subsystem"
20 Driver for Xilinx MIPI CSI-2 Rx Subsystem. This is a V4L sub-device
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6qdl-dhcom-drc02.dtsi14 * pins SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2
15 * Tx and Rx are routed to the DHCOM UART1 rts/cts pins. Therefore the micro SD
72 * Due to the use of can2 the signals for can2 Tx and Rx are routed to
110 * can2 Tx and Rx.
/openbmc/linux/Documentation/networking/device_drivers/ethernet/huawei/
H A Dhinic.rst17 HiNIC devices support MSI-X interrupt vector for each Tx/Rx queue and
108 Rx Queues - Logical Rx Queues that use the HW Receive Queues for receive.
109 The Logical Rx queue is not dependent on the format of the HW Receive Queue.
112 hinic_dev - de/constructs the Logical Tx and Rx Queues.
/openbmc/u-boot/doc/device-tree-bindings/net/
H A Daltera_tse.txt12 "rx_csr" : xDMA Rx dispatcher control and status space region
13 "rx_desc": MSGDMA Rx dispatcher descriptor space region
14 "rx_resp": MSGDMA Rx dispatcher response space region
18 "rx_irq": xDMA Rx dispatcher interrupt
/openbmc/linux/drivers/phy/cadence/
H A DKconfig26 tristate "Cadence D-PHY Rx Support"
31 Support for Cadence D-PHY in Rx configuration.
/openbmc/linux/Documentation/networking/
H A Dnapi.rst23 of event (packet Rx and Tx) processing.
66 Rx packets. Rx processing is usually much more expensive.
68 In other words for Rx processing the ``budget`` argument limits how many
69 packets driver can process in a single poll. Rx specific APIs like page
77 skb Tx completions and no Rx or XDP packets.
161 (queue pair is a set of a single Rx and single Tx queue).
164 or Rx and Tx queues can be serviced by separate NAPI instances on a single
173 to utilize 3 interrupts, 2 Rx and 2 Tx queues.
H A Dnetif-msg.rst29 - 4 Tx and Rx frame error messages, and abnormal driver operation
31 - 6 Status on each completed Tx packet and received Rx packets
32 - 7 Initial contents of Tx and Rx packets
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Damd-xgbe.txt8 - SerDes Rx/Tx registers
18 correct Rx interrupt watchdog timer value on a DMA channel
28 - amd,per-channel-interrupt: Indicates that Rx and Tx complete will generate
H A Dsff,sfp.yaml60 GPIO phandle and a specifier of the Rx Signaling Rate Select (AKA RS0)
61 output gpio signal, low - low Rx rate, high - high Rx rate Must not be
/openbmc/linux/Documentation/devicetree/bindings/mailbox/
H A Dti,secure-proxy.yaml47 Contains the interrupt name information for the Rx interrupt path for
54 Contains the interrupt information for the Rx interrupt path for secure
/openbmc/qemu/hw/char/
H A Dtrace-events83 exynos_uart_dmabusy(uint32_t channel) "UART%d: DMA busy (Rx buffer empty)"
90 exynos_uart_rx_fifo_reset(uint32_t channel) "UART%d: Rx FIFO Reset"
95 exynos_uart_rx(uint32_t channel, uint8_t ch) "UART%d: Rx 0x%02"PRIx32
96 exynos_uart_rx_error(uint32_t channel) "UART%d: Rx error"
98 exynos_uart_rxsize(uint32_t channel, uint32_t size) "UART%d: Rx FIFO size: %d"
100 exynos_uart_rx_timeout(uint32_t channel, uint32_t stat, uint32_t intsp) "UART%d: Rx timeout stat=0x…
/openbmc/linux/Documentation/userspace-api/media/drivers/
H A Dmax2175.rst40 The Rx mode controls a number of preset parameters of the tuner like
42 provided under one single label called Rx mode in the datasheet. The
/openbmc/linux/Documentation/devicetree/bindings/soc/ti/
H A Dkeystone-navigator-dma.txt47 - Rx DMA channel configuration register region (rxchan).
49 - Rx DMA flow configuration register region (rxflow).
57 - ti,loop-back: To loopback Tx streaming I/F to Rx streaming I/F. Used for
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dmicrochip,sparx5-serdes.yaml20 * Rx variable gain control
21 * Rx built-in fault detector (loss-of-lock/loss-of-signal)
/openbmc/linux/Documentation/devicetree/bindings/ata/
H A Dsnps,dwc-ahci-common.yaml31 PM-alive clock, RxOOB detection clock, embedded PHYs reference (Rx/Tx)
103 description: Maximal size of Rx DMA transactions in FIFO words
/openbmc/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-k2g-netcp.dtsi83 <0x4012000 0x400>, /* 32 Rx channels */
85 <0x4013000 0x400>; /* 32 Rx flows */

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