Searched refs:RVG (Results 1 – 4 of 4) sorted by relevance
| /openbmc/qemu/target/riscv/tcg/ |
| H A D | tcg-cpu.c | 344 bool send_warn = cpu_misa_ext_is_user_set(RVG); in riscv_cpu_validate_g()
419 if (riscv_has_ext(env, RVG)) { in riscv_cpu_validate_set_extensions()
1055 MISA_CFG(RVG, false),
1341 riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV); in riscv_init_max_cpu_extensions()
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| /openbmc/qemu/target/riscv/ |
| H A D | cpu.c | 45 RVC, RVS, RVU, RVH, RVJ, RVG, RVB, 0};
535 riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU); in rv64_thead_c906_cpu_init()
567 riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH); in rv64_veyron_v1_cpu_init()
1411 MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
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| H A D | cpu.h | 70 #define RVG RV('G') macro
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| H A D | csr.c | 1698 val &= ~RVG; in write_misa()
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