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Searched refs:RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_sh_mask.h9384 #define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT 0x10 macro
H A Dgfx_8_1_sh_mask.h9932 #define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT 0x10 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h27217 #define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h28827 #define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT … macro
H A Dgc_9_1_sh_mask.h28499 #define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT … macro
H A Dgc_9_4_3_sh_mask.h30568 #define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT … macro
H A Dgc_9_4_2_sh_mask.h14390 #define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT … macro
H A Dgc_11_0_0_sh_mask.h37985 #define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h36332 #define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h39718 #define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h36411 #define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT … macro